Each SX instruction that accesses a data memory register contains a 5-bit field in the instruction opcode that specifies the register to be accessed. The abbreviation fr (file register) represents the 5- bit register address designator. For example, the instruction description mov fr,W means that a 5-bit value or label must be substituted for fr in the instruction, such as mov $0F,W (to move the con- tents of the working register W into file register 0Fh).
There are three different addressing modes, called the indirect, direct, and semi-direct modes. The addressing mode used for register access depends on the 5-bit fr value used in the instruction:
indirect mode: fr = 00h
direct mode (fr bit 4 = 0): fr = 01h through 0Fh
semi-direct mode (fr bit 4 = 1): fr = 10h through 1Fh
Figure 2-2 illustrates the data memory addressing scheme.
For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed.
FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data memory for indirect addressing. In this mode, the global register bank and Bank 1 through Bank F are accessible. Bank 0 is not accessible.
For direct addressing (fr=01-0F), the value of fr itself specifies the register to be accessed, and the FSR register is ignored. For this addressing mode, only the global register bank is accessible. To gain access to any other bank, you must use either indirect or semi-direct addressing.
For semi-direct addressing (fr=10-1F), the bank number is selected by the four high-order bits of FSR, and the register within that bank is selected by the four low-order bits of fr. In other words, the register address is obtained by combining the four high-order bits of FSR with the four low-order bits of fr. In this addressing mode, the low-order bits of FSR are ignored. Bank 0 through Bank F are accessible, but the global register bank is not accessible.
Figure 2-2 shows how register addressing works in the indirect, direct, and semi-direct modes. The 16 global registers are always accessible by direct addressing, regardless of what is contained in the FSR register. The global registers are also accessible with indirect addressing, but they are not accessible with semi-direct addressing. Of the 16 global registers, nine are special-purpose registers (RTCC, PC, STATUS, and so on), and six are general-purpose registers. Location 00 is used for indirect address- ing (INDF). All of the registers in Bank 0 though Bank F are general-purpose registers. To change the contents of the FSR register, the program can either write an eight-bit value to the FSR register or use the bank instruction. The bank instruction writes the three high-order bits (4, 5, and 6) in the FSR register. Bit 7 of FSR is used to select the upper or lower bank of memory banks. Thus, to change from one upper bank to another, only a single bank instruction is required. To change from one upper bank to a lower bank, the bank instruction must be followed by setb FSR.7.
|file: /Techref/scenix/reg/fsrsemi.htm, 3KB, , updated: 2004/12/13 18:13, local time: 2022/8/9 13:50,
|©2022 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://massmind.org/Techref/scenix/reg/fsrsemi.htm"> SX48/52BD Addressing Modes and FSR Register</A>
|Did you find what you needed?|
Welcome to massmind.org!
Welcome to massmind.org!