mem dram ckt5

;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    SAMPLE Z280 DESIGN - SYSTEM TIMING GENERATOR
PATTERN  PROTO
REVISION A
AUTHOR   TIM OLMSTEAD
COMPANY  
DATE     08/29/96

CHIP  PROTO  PAL16L8

;---------------------------------- PIN Declarations ---------------
PIN  1          MREQ                            ; INPUT 
PIN  2          CASIN                           ; INPUT 
PIN  3          A23                             ; INPUT 
PIN  4          A22                             ; INPUT 
PIN  5          RD                              ; INPUT 
PIN  6          IORQ                            ; INPUT 
PIN  7          M1                              ; INPUT 
PIN  8          RFSH                            ; INPUT 
PIN  9          WR                              ; INPUT 
PIN  10         GND                             ; INPUT 
PIN  11         A07                             ; INPUT
PIN  12         PIN12                COMBINATORIAL ; OUTPUT
PIN  13         PIN13                COMBINATORIAL ; OUTPUT
PIN  14         PIO                  COMBINATORIAL ; OUTPUT
PIN  15         RAS                  COMBINATORIAL ; OUTPUT
PIN  16         CAS                  COMBINATORIAL ; OUTPUT
PIN  17         SRAM                 COMBINATORIAL ; OUTPUT
PIN  18         ROM                  COMBINATORIAL ; OUTPUT
PIN  19         RAMSEL               COMBINATORIAL ; OUTPUT
PIN  20         VCC                             ; INPUT 

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

/RAMSEL = /MREQ * A23 * RFSH     ; DECODE UPPER 8MB FOR DRAM
        + /MREQ * /RFSH          ; REFRESH

/ROM = /A23 * /A22 * /MREQ * /RD ; READ IN FIRST 4MB BLOCK IS ROM

/SRAM = /A23 * A22 * /MREQ       ; ANY ACCESS IN SECOND 4MB IS SRAM


/RAS = /MREQ * A23 * RFSH        ; DECODE UPPER 8MB FOR DRAM
     + /MREQ * /RFSH * /CASIN    ; REFRESH

/CAS = RFSH * /CASIN * /RD       ; NORMAL CAS FOR MEMORY READ
     + RFSH * /CASIN * /WR       ; HOLD OFF CAS FOR EARLY WRITES
     + /RFSH * /MREQ             ; CAS GOES LOW EARLY FOR REFRESH

/PIO = /IORQ * M1 * A07          ; ALL I/O GOES TO PIO FOR NOW

;----------------------------------- Simulation Segment ------------
SIMULATION

;-------------------------------------------------------------------

file: /techref/mem/dram/ckt5.pds, 2KB, , updated: 1996/9/22 08:57, local time: 2009/1/7 15:21,

^{38.103.63.57:LOG IN}

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