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'[AD]Hardware design engineer - 7 yrs experience - '
2009\04\10@072904 by Mohamed Ismail Bari

picon face
Hello all,

I am a hardware engineer looking for appropriate hardware design opennings
in the UK. Attached is my detailed resume. (Pls excuse me as it is very
lengthy).

If you are interested in my profile pls shoot me an email.

Thanks you,
-Ismail


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Resume of MOHAMED ISMAIL BARI -> spam_OUTizmileTakeThisOuTspamyahoo.com , .....izmileKILLspamspam@spam@gmail.com

Objective
To obtain a senior position in electrical engineering that utilizes my seven
years of experience in the following areas - electronic system design,
package modeling and package design, EMI, EMC, product reliability, and my
bachelor's degree in electronics and communication.

Areas of Specialization
* Analog and Digital circuit design
* High speed PCB design
* Knowledge of FPGA design using HDL
* 8051/PIC based Micro controllers
* C, C++ and Assembly language

Technical Skills
Programming Languages       : C, C++
GUI Tools                             : Visual C++, Visual Basic
Circuit Simulators                 : HSPICE, PSPICE
Schematic Capture Tools      : Orcad 9.2, PCAD 2002, Protel 99SE,
PCB Design Tools                : Orcad 9.2, PCAD 2002, Protel 99SE, Allegro
14.0, Spectra 13.0
Signal Integrity                     : Hyperlynx, SigXplorer 14.0
Version Control Tools            : Visual Source Safe (VSS) & PVCS.
Communication Protocols     : TCP/IP, ISO14443 (Contactless reader
protocol),
                                            ISO7816 (Contact reader
protocol)
Communication Bus            : PCI, ISA, I2C, SPI, RS485, JTAG, USB
Test Equipments                 : Oscilloscopes, Logic Analyzer, Impedance
Analyzer

Professional Experience

Period         : Aug 2005 - Present
Company Name   : SCM Microsystems (India)
Designation    : Project Leader (Hardware)
Field of Work  : RFID reader design and development

Period         : Dec 2003 - Aug 2005
Company Name   : Intel Corporation (India)
Designation    : Component Design Engineer
Field of Work  : Power Delivery Electrical Analysis /Package design

Period         : Jul 2001 - Dec 2003
Company Name   : HCL Technologies (India)
Designation    : Member Technical Staff
Field of Work  : High speed Board Design/FPGA design using Verilog

Academic Qualification
Period         : 1997 - 2001
Degree         : Bachelor of Engineering (Electronics and Communication)
University     : Bharathiyar University (Coimbatore, India)

Strengths
* Highly proficient in C, C++, Visual C++, Assembly language
* Good digital/analog circuit designing capability
* Good signal integrity analysis skills
* Knowledge of EMI, EMC and reliability concepts
* Comfortable with PCB/Schematic tools
* Good knowledge in Design for Testability/Manufacturability (DFT/DFM)

Employment Status in UK
* Authorized to work for any employer in the UK.
* Visa Type: HSMP (General Tier 1 Migrant)
* Visa Valid From: 01 - Nov - 2008
* Visa Valid Until: 01 - Nov - 2011

Location
* Currently in the UK looking for appropriate hardware design job

Availability
* Immediately available
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Project Experience
RFID Contactless Smartcard Reader Development for electronic-passport
application
Company : SCM Microsystems
Duration : Sept'05 - Present
Travel :
* e-Passport Interoperability Show - Berlin, Germany
* Smart card reader supervision on mass production - Singapore and Batam,
Indonesia
Client : Datacard, 3M, Zebra
Performed as a Project Lead for Contact and Contactless smartcard reader
hardware designs.
Responsibility :
* Overall hardware design for Contact and Contactless smartcard readers
using 8051 based USB microcontrollers
* Managing a team of two Junior engineers
* End-to-end responsibility for two Contactless smartcard reader products.
* Liaising with cross-functional teams for product mass production
* Approving identified components and BOM release for mass production
* Product FCC, CE and UL certifications
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RFID Dual Antenna ePassport Reader
Company : SCM Microsystems
Duration : Jan'07 - Jul '07
Travel : U.S.A, Boston - For product development
Client : Viisage, L1 identification
This project is an ePassport reader incorporating two reader antennae close
to each other. The greatest challenge in this design is to avoid
inter-antenna coupling between the two antennae. To avoid inter-antenna
coupling, a shorting mechanism was implemented where the inactive antenna
will be electrically detuned when the other antenna is active.
Responsibility :
* Hardware design and software development support
* Project management and tracking
* Realized a working prototype and delivered it to the customer
* Sign-off from the customer for proceeding with the mass production.
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Handheld RFID Reader - TAN Generator
Company : SCM Microsystems
Duration : Oct'06 - Dec '06
Travel : None
Client : MasterCard
This project is a handheld battery operated Contactless reader used for
Transaction Access Number (TAN) generation. The greatest challenge was on
the low power design as the device operates on two AA batteries. Further,
the project had a very aggressive timeline. Successful completion of this
project within an aggressive timeline earned a good reputation in the
company.
Responsibility :
* Hardware and software design
* Project management and tracking
* Coordinated software design which was developed by a consultant in Germany
* Realized a working prototype within a short time
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Network Processor Power Delivery Analysis
Company : Intel Corporation
Duration : Dec '03 - Aug'05
Team size : Individual
Environment : Windows NT
Travel : Arizona, U.S.A
Performed power delivery analysis for Microprocessor I/O interface to ensure
efficient power delivery even under worst-case transient switching.
Electrical modeling was done using HSPICE. The entire power delivery network
to the microprocessor is modeled as discrete elements in HSPICE. Simulations
were done and recommendations were made to circuit designers and package
designers on the amount of on-die/on-package capacitance requirements.
Responsibility :
* To make package design/layout recommendation to control power supply
noises in the microprocessor
* To recommend the number of package capacitors
* To recommend the amount of capacitance needed on the processor die
* Electrical modeling and analysis of package and processor die in HSPICE
* Provide design recommendations to package and circuit design team
* Developed an in-house tool using Visual C++ for easy electrical modeling
of the transient load
Tools used :
* Synopsys HSPICE U-2003.3v1
* Cougar V2.8.1 (Intel Corporation's internal tool)
* AvanWaves
* Ansoft Q3D extractor ver5.0
* Ansoft 2D extractor ver5.0
* Ansoft Links ver2.2
* APD ver14.0 (Advanced Package Design by Cadence)
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Fiber Channel Simulator
Company : HCL Technologies
Client : McData, Colorado, U.S.A
Duration : Oct '03 - Dec'03
Team size : 3
Environment : Windows NT
Travel : None
The primary objective of this project is to develop a PCI based add-on card.
The hardware is used to send FC data over optical fiber at a data rate of
10Gbps. However, the hardware also supports 1Gbps, 2Gbps and 4Gbps. Most of
the functionality is implemented in software. The hardware just
transmits/receives the FC data and presents it to the higher layers.
Responsibility :
* Assisting in Overall design
* Component Selection
* Developed Schematics
Tools used :
* Mentor Board Station
* Modelsim 5.0
* Synplify pro 5.1
* Xilinx Foundation series
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Ethernet / LAC / OEB Interface Board Design
Company : HCL Technologies
Client : Rockwell Collins passenger systems, California, U.S.A
Duration :   Nov '02 - Sept '03
Team size :  4
Environment : Windows NT
Travel : California, U.S.A
The eTES Area Distribution Box (eADB) is part of the eTES In-Flight
Entertainment System. This is a Motorola MP860T based card. The eADB forms
the backbone of the IFE Cabin Distribution Network for Boeing and Airbus
line fit airplanes, and for retrofit applications on in-service Boeing and
Airbus aircrafts.
Responsibility :
* Overall design
* Designed power sequencing circuits
* Developed schematics
* Performed analog circuit analysis and simulations
* Assisted PCB component placement and routing
* Developed diagnostics for board validation in C language.
* Performed board bring-up at onsite.
* Assisted in EMI testing of the boards.
* Assisted in board manufacturing in procuring parts.
Tools used :
* NC VHDL, Modelsim
* PCAD 2001 Schematic capture tool
* PCAD 2001 PCB layout and routing tool
* Spectra - Auto routing tool
* Microware OS9 builder - OS9000 application builder
* CircuitMaker 2001 - Circuit simulation tool
* Simetrix 4.1c - Circuit simulation tool
* PVCS - Version control system
* PVCS Tracker - Bug Tracking system
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Network Processor based Line Card for Ethernet over VDSL Applications
Company : HCL Technologies
Client : Accordion Networks, California, U.S.A
Duration :  Jun '02  - Oct '02
Team size : 5
Environment : Windows NT
Travel : None
Designed and developed a board for Ethernet-over-VDSL communication. The
board uses INTEL Network Processor (IXP1200) for processing and transmitting
VDSL packets received from the VDSL end through the INTEL IXF440 MAC (100
Mbps) to the back plane. The back plane consists of a cross-stream switch
fabric (Vitesse VSC870 - VSC880) for switching the packets to other line
cards. The whole process could work in the other way (i.e from back plane to
the VDSL end). The packet routing rules were enforced by the application
running in the Network processor. VxWorks was used as the real time
operating system in which the applications run. The board also employs an
Ethernet data path using INTEL 82559. The application code was downloaded to
the flash memory devices through the Ethernet data path.
Responsibility :
* Prepared system requirements document
* Prepared High level design document
* Identified required components
* Calculated overall power budget.
* Created symbols
* Developed Schematics
* Reviewed PCB symbols
* Guided component placement and routing.
* Analyzed signal quality for critical signals using IBIS models (Signal
integrity analysis)
* Performed On-site board bring up at the customer site in USA.
Tools used :
* Orcad 9.25 - Schematic capture tool
* Allegro v14.0  - PCB layout and routing tool
* SigXplorer - Signal Integrity analysis tool
* Spectra - Auto routing tool
* Winriver VxWorks Compiler - For building diagnostics bundle with the Board
Support Package (BSP).
* PVCS - Version control system
* PVCS Tracker - Bug Tracking system
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OC-48 I/O Board Design
Company : HCL Technologies
Client : IPolicy Networks, California, U.S.A
Duration :  Dec '01 - May'02
Team size : 3
Environment : Windows NT
Travel : None
This board design was intended to convert FOCUS bus (Vitesse proprietary
bus) signals into OC-48 optical signals. The design consists of two channels
of optical communication where two FPGA devices were used. The data signal
from the FOCUS bus was converted into POS-PHY level 3 signals by the FPGA.
Thereafter, the POS-PHY signal was processed by the optical framer/mapper
(VSC9142), which converts the electrical signal to optical signal. Since
data rate was very high, signal integrity analysis was done for routing the
signals.
Responsibility :
* Prepared High-level design document
* Identified required components
* Calculated overall power budget
* Created schematics symbols
* Developed schematics
* Integrated schematics
* Reviewed PCB symbols
* Guided component placement and routing.
* Collected IBIS models for signal integrity analysis
* Analyzed signal quality for critical signals (Signal Integrity)
* Generated Signal Integrity report.
Tools used :
* Orcad 7.1.25 - Schematic capture tool
* Allegro v13.0 - PCB layout and routing tool
* SigXplorer - Signal Integrity analysis tool
* Spectra - Auto routing tool
* PVCS - Version control system
* PVCS Tracker - Bug Tracking system
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POS PHY Level-3 Bus to FOCUS Bus Bridge FPGA
Company : HCL Technologies
Client : Vitesse Semiconductors, California, U.S.A
Duration : Jul '01 - Nov '01
Team size : 3
Environment : Solaris 7, 8
Travel : None
The FPGA converts POS-PHY level 3 bus signals to FOCUS bus signals and vice
versa. FOCUS bus is a proprietary bus used in Vitesse semiconductors in
their Network processor product line. The FPGA is intended to seamlessly
integrate the POS-PHY bus to the FOCUS bus at a data rate of 100Mbps.
Responsibility :
* Designed and coding one of the modules in the FPGA
* Validated the entire design on silicon
* Design challenge was validating the RTL at 100 MHz.
Tools used :
* Synplify 5.1 - FPGA synthesis tool
* Xilinx Foundation Series 4.0 - FPGA place and route tool
* PVCS - Version control system
* PVCS Tracker - Bug Tracking system
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