Post by thread:[EE]: JK Flip Flop will not div by 2!

Colleagues: I have a circuit with a 74LS73 wired as a toggle flip flop, or div by 2. In order to do that, you tie the J and K to +5V. It works for the most part, until I drop the frequency below 30 hertz. The darned thing just packs up and stops toggling the output. Raise the frequency a tad, and it start up again. I have decoupling on the part. I have fast (reasonably) rise times. The problem happens in circuit and out of circuit. I am using the LS family because I can (presumably) still get 54LS family parts. The customer wants to have mil parts in his product. I may try HC logic next, jsut to see if it is the LS family. Any grand ideas? Thanks Chris Eddy -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

How are you driving it? The LS version is edge triggered so if the rising edge is too slow or noisy you might get strange operation. If you are driving it via a capacitor somewhere in the chain (eg coupling from a function generator) you might just need more capacitance. - To state the obvious! Richard P -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

Well, it happens under two conditions.. In the circuit, where it is driven by another LS part, and on a breadboard, where it is driven by the TTL output on my func gen. Signal on the clock pin of the 73 appears to be clean, but then, just how fast of a rise time do I need? Chris Richard Prosser wrote: {Quote hidden}> How are you driving it? > The LS version is edge triggered so if the rising edge is too slow or noisy > you might get strange operation. > If you are driving it via a capacitor somewhere in the chain (eg coupling > from a function generator) you might just need more capacitance. - To state > the obvious! > > Richard P > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

Just looking at a databook, their test circuit specifies an input transition low-high of 15nS and a transition high - low of only 6nS!. (at a repitition frequencuy of 1MHz). I'm sure they will work a lot slower than this. Just as another possibility - is the supply stable. If there is insufficient capacitance or drive on the line it may sag under one state or the other (loading dependent) and drop out of the operating band. I guess this is similar to decoupling but at the low end of the spectrum. Have you scoped the output - does it just stop - or is there noise or glitches where you'd expect transistions? I've got a dim recollection of coming accross this type of problem before - but can't remember the fix! Richard P +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Chris Eddy <spam_OUTceddyTakeThisOuTNB.NET> To: .....PICLISTKILLspam@spam@MITVMA.MIT.EDU Sent by: pic cc: microcontrolle Subject: Re: [EE]: JK Flip Flop will not div by 2! r discussion list <PICLIST@MITVM A.MIT.EDU> 04/08/00 12:37 Please respond to pic microcontrolle r discussion list Well, it happens under two conditions.. In the circuit, where it is driven by another LS part, and on a breadboard, where it is driven by the TTL output on my func gen. Signal on the clock pin of the 73 appears to be clean, but then, just how fast of a rise time do I need? Chris Richard Prosser wrote: > How are you driving it? > The LS version is edge triggered so if the rising edge is too slow or noisy > you might get strange operation. > If you are driving it via a capacitor somewhere in the chain (eg coupling > from a function generator) you might just need more capacitance. - To state > the obvious! > > Richard P > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

On 3 Aug 2000, at 19:43, Chris Eddy wrote: > Colleagues: > > I have a circuit with a 74LS73 wired as a toggle flip flop, or div by > 2. In order to do that, you tie the J and K to +5V. It works for the > most part, until I drop the frequency below 30 hertz. The darned thing > just packs up and stops toggling the output. Raise the frequency a tad, > and it start up again. I have decoupling on the part. I have fast > (reasonably) rise times. The problem happens in circuit and out of > circuit. > > I am using the LS family because I can (presumably) still get 54LS > family parts. The customer wants to have mil parts in his product. > > I may try HC logic next, jsut to see if it is the LS family. > > Any grand ideas? > Thanks > Chris Eddy Its probably not the problem here but I went quietly mad trying to figure out why I couldnt get a monostable I.C. to work once. I eventually figured out the data book had the wrong pin outs!!!!!! Good old Nat Semi. Have you tied set and clear to the appropriate rails and not just left them 'flapping in the wind'? _____________________________ Lance Allen Technical Officer Uni of Auckland Psych Dept New Zealand http://www.psych.auckland.ac.nz _____________________________ -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics

At 07:43 PM 8/3/00 -0400, you wrote: >I may try HC logic next, jsut to see if it is the LS family. > >Any grand ideas? For LS logic, the input transition should be faster than 15ns/volt over the range 0.4 to 2.4V. HC logic is much more tolerant, requiring only 110ns/volt. Note that on the '73, the rise time is not as important as the fall time. Could it be that you have some long (more than 6-12") wires in this system? Best regards, =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speffKILLspaminterlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.bluecollarlinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

This is not happening! Any flip-flop divide by 2 even in trench ! you have more than 50MHz there ? Vasile On Fri, 4 Aug 2000, Spehro Pefhany wrote: {Quote hidden}> At 07:43 PM 8/3/00 -0400, you wrote: > > >I may try HC logic next, jsut to see if it is the LS family. > > > >Any grand ideas? > > For LS logic, the input transition should be faster than 15ns/volt > over the range 0.4 to 2.4V. HC logic is much more tolerant, > requiring only 110ns/volt. Note that on the '73, the rise time > is not as important as the fall time. > > Could it be that you have some long (more than 6-12") wires > in this system? > > Best regards, > > > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > Spehro Pefhany --"it's the network..." "The Journey is the reward" > .....speffKILLspam.....interlog.com Info for manufacturers: http://www.trexon.com > Embedded software/hardware/analog Info for designers: http://www.speff.com > Contributions invited->The AVR-gcc FAQ is at: http://www.bluecollarlinux.com > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > > -- > http://www.piclist.com hint: The PICList is archived three different > ways. See http://www.piclist.com/#archives for details. > -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

>I am using the LS family because I can (presumably) still get 54LS >family parts. The customer wants to have mil parts in his product. You should have no problem getting MIL versions of 54HC, you may have great difficulty with 54LS. check http://www.dscc.dla.mil/ for parts to mil specs and the suppliers. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

> I have a circuit with a 74LS73 wired as a toggle flip flop, or div by > 2. In order to do that, you tie the J and K to +5V. It works for the > most part, until I drop the frequency below 30 hertz. The darned thing > just packs up and stops toggling the output. Raise the frequency a tad, > and it start up again. I have decoupling on the part. I have fast > (reasonably) rise times. The problem happens in circuit and out of > circuit. The 74LS73 differs from some of the other '73 varieties in that holding clock low forces Q high, regardless of J and K. It only toggles on the FALLING EDGE of clock. ***************************************************************** Olin Lathrop, embedded systems consultant in Devens Massachusetts (978) 772-3129, EraseMEolinspam_OUTTakeThisOuTcognivis.com, http://www.cognivis.com -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

Tie J to /Q and K to Q. 'Reasonably fast' flanks are famous last words in digital design afaik ;-). Reasonably fast for LS TTL is probably 150 nsec or better flanks. Even with J and K tied as above it might not work with slow flanks. imho use the J & K tie shown and improbve the trigger flank using an amplifier (a single gate will probably do). hope this helps, Peter -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

At 11:54 AM 8/4/00 +0300, you wrote: > This is not happening! Any flip-flop divide by 2 even in trench ! > you have more than 50MHz there ? > Vasile Not if the signal integrity to the clock is not maintained. Tr and Tf at the clock must be < 30nsec (measured from 2.4 V to 0.4V) (especially Tf) for reliable LSTTL operation. Reference: TI application notes And, there must be only one edge, or it may be appearing to not work, but actually be double counting. Long ground and signal leads (or even a faulty ground lead) could cause this sort of erratic operation. Is there something else going on here? Is that FF switching something else? If so, try disconnecting it temporarily. Best regards, =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speffspam_OUTinterlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.bluecollarlinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

Right, here is what I have tried so far. I added tons of decoupling to my breadboard. No difference. My scope shows that I have a sub 10nS rise time. No big problem. I tied J and K to /Q and Q like you suggested, and I got better results down to operating at 11 hertz. I sure would like it to be fully static, IE work down to 0 hertz. I must order the HC version, so I am out of luck for now. Thanks to Alan for the advice that 54HC is easier than 54LS. Mil spec is alien territory for me. Chris Eddy "Peter L. Peres" wrote: > Tie J to /Q and K to Q. 'Reasonably fast' flanks are famous last words in > digital design afaik ;-). Reasonably fast for LS TTL is probably 150 nsec > or better flanks. Even with J and K tied as above it might not work with > slow flanks. imho use the J & K tie shown and improbve the trigger flank > using an amplifier (a single gate will probably do). > -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.

> 11Hz, 10 nsec flanks That is a bit too fast imho. Is there any overshoot or undershoot ? Do you drive it with LSTTL or rail to rail (don't !). If you drive rail to rail it may help to limit the H level to Vcc - 0.8V. It may also help to add a small resistor (~100R) and a 47 pF cap to GND in series with the clock wire. Just in case there is ringing. I assume that you did try other chips from the same series ? Who is the manufacturer of the chips ? ;) Yes, I've had it that way too. <g> Peter -- http://www.piclist.com hint: To leave the PICList @spam@piclist-unsubscribe-requestKILLspammitvma.mit.edu>

Alas, I have switched over to a 74LS74 dual D type, wired with /Q to D. This config works like a real trooper all the way down to single toggles. I hate to do it, but I will leave the JK debacle to the mystery file. I must move this project on, so I will take the easy way out. 'Sides, I noticed too late that anything XX73 is rarely on the list in catalogs. But XX74 is common. Live and learn! Chris Eddy "Peter L. Peres" wrote: {Quote hidden}> > 11Hz, 10 nsec flanks > > That is a bit too fast imho. Is there any overshoot or undershoot ? Do you > drive it with LSTTL or rail to rail (don't !). If you drive rail to rail > it may help to limit the H level to Vcc - 0.8V. It may also help to add a > small resistor (~100R) and a 47 pF cap to GND in series with the clock > wire. Just in case there is ringing. > > I assume that you did try other chips from the same series ? Who is the > manufacturer of the chips ? ;) Yes, I've had it that way too. <g> > > Peter > > -- > http://www.piclist.com hint: To leave the PICList > KILLspampiclist-unsubscribe-requestKILLspammitvma.mit.edu -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]: PIC only [EE]: engineering [OT]: off topic [AD]: advertisements