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'[EE]: recording of digital signals'
I'm in desperate need of a small tester to check digital (5V level) signals
with a resolution of 1µs. The main problem is that I get about 12 seconds of
data at a data rate of 250 kbit/s I have to find spurious errors within this
data stream. I'm thinking of something with a big memory (12
seconds/1µs=12Mb) which content can be send to a PC for checking (some sort
of analysis software needed here). No need for realtime visualisation, the
data packets are sent with long pauses in between (> 5 minutes).
Thanks for any help!
On Tue, 2009-04-21 at 10:31 +0200, Peter Feucht wrote:
> I'm in desperate need of a small tester to check digital (5V level) signals
> with a resolution of 1Âµs. The main problem is that I get about 12 seconds of
> data at a data rate of 250 kbit/s I have to find spurious errors within this
> data stream. I'm thinking of something with a big memory (12
> seconds/1Âµs=12Mb) which content can be send to a PC for checking (some sort
> of analysis software needed here). No need for realtime visualisation, the
> data packets are sent with long pauses in between (> 5 minutes).
> Any idea?
> Thanks for any help!
Pic connected to an SD card. Lots of examples out there.
As an alternative, some of the later USB PICs support limited host mode,
plug a USB stick in and capture away. MChip has a 24F dev kit that
basically does exactly what you are describing.
250kb serial stream is VERY fast for a 20Mhz PIC. It needs to be
operating at 40Mhz at LEAST regardless of type.
I'd capture it into a RAMTRON SPI device, it can certainly keep up..
On 4/21/09, Herbert Graf <gmail.com> wrote: hkgraf
Bob Axtell opined:
>250kb serial stream is VERY fast for a 20Mhz PIC. It needs to be
>operating at 40Mhz at LEAST regardless of type.
>I'd capture it into a RAMTRON SPI device, it can certainly keep up..
Actually, the OP wants to read the data at 1MHz, not 250KHz!
Even so, as Olin indicated, this isn't all that fast. You simply set the
MSSP up in sync mode and use a PWM to generate a clock for it.
Assume: 20MHz clock on PIC, this is a 5MHz instruction rate.
Set up a PWM with a period of 5 instructions and a duty cycle of 50%. This
will give you a 1Mhz clock.
Feed the PWM output back into the MSSP clock pin.
You will now get a byte of data every 5*8 = 40 instructions.
With an appropriate interface to an SRAM you can easily write bytes that
fast to it.
I would set up some counters on the SRAM address lines. Then the kernel of
instructions to grab and write a bit could be as simple as:
<wait for and get byte from MSSP>
movwf PORTD ; put data byte on port
bcf PORTB,NWRITE ; activate the write strobe
bsf PORTB,NWRITE ; clear the write strobe
bsf PORTB,CLOCK ; clock the counters
bcf PORTB,CLOCK ; clear the counter clock
Even with the NOPs to reduce RMW issues and provide a nice slow cycle for
the SRAM, that leaves you lots of time for other stuff like counting down
the number of samples to be stored.
Of course, this would be a non-starter in "C" :-)
-- Bob Ammerman
Bob Axtell wrote:
> 250kb serial stream is VERY fast for a 20Mhz PIC.
Yet I've captured a 1Mbit/sec digital stream on a 16F877, which then wrote
it to external static RAM. The trick is to use the MSSP in synchronous
serial mode so that the firmware deals with a byte every 40 instructions
instead of a bit every 5. 40 instructions was tight, but it did work.
If doing this on a 18F2550 you get 96 instruction cycles per byte, which
sounds like plenty.
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014. Gold level PIC consultants since 2000.
part 1 475 bytes content-type:text/plain; (decoded 7bit)
Bob Ammerman wrote:
> I would set up some counters on the SRAM address lines. Then the
> kernel of instructions to grab and write a bit could be as simple as:
That would definitely simplify things, but it can be done in the PIC too.
The project where I did this was a floppy disk drive emulator. The 16F877
code for the write loop from 2001 is attached. It took some careful cycle
counting but all the logic got crammed in there.
part 2 6314 bytes content-type:text/plain;
; Write loop. The loop runs once for each byte read from the
; synchronous serial port and written to the external RAM. The loop
; must not be more than 40 cycles long on average, else the serial
; port will get overrun
; Register useage:
; REG2,REG1,REG0 - RAM address of the next byte to write. This
; is incremented by 1 for each byte, except that it is wrapped
; back to the track start address at the start of the track. The
; start of the track is indicated by timer 1 wrapping back to 0.
; REG5,REG4,REG3 - RAM address for the start of the track.
dbankis memwr_reg ;indicate bank settings in effect at end of loop
; Check all the input lines from the floppy controller. This loop is
; aborted if any of these lines change from the conditions that
; caused this loop to be run. The saved conditions are in LSTAT.
movf read_reg, w ;read port containing all the input bits
xorwf lstat, w ;compare to saved input bits
skip_z ;no changes ?
goto wr_ichan ;one or more input bits changed
wr_nstat ;jump here to continue with new LSTAT
;--- +4 cycles, 4 total ---
; Make the RAM address of the next byte to write by incrementing the
; old address by 1.
; This section is optimized for the least average cycles. A carry from
; the low byte into the next will only happen every 256 times thru here.
incf reg0 ;increment byte 0
skip_nz ;no carry into byte 1 ?
call wr_carr ;go handle the carry
;--- +3 cycles, 7 total ---
; Check for wrap back to the beginning of the track. The CCP1 module
; is used in compare with special trigger mode so that timer 1 always
; contains the updated byte offset into the current track data in RAM.
; The CCP1 interrupt flag is therefore set whenever the track is
btfsc pir1, ccp1if ;not just wrapped around to start of track ?
call wr_wrap ;go handle wrap back to start of track
;--- +2 cycles, 9 total ---
; Write the address of the byte to write to the address latches.
wr_wadr ;write loop is entered here after init
movf reg0, w ;get address byte 0
movwf d0_reg ;write it to the data bus
bsf ldadr0_pin ;write the data bus value to the address latch
movf reg1, w ;get address byte 1
movwf d0_reg ;write it to the data bus
bsf ldadr1_pin ;write the data bus value to the address latch
movf reg2, w ;get address byte 2
movwf d0_reg ;write it to the data bus
bsf ldadr2_pin ;write the data bus value to the address latch
;--- +12 cycles, 17 total ---
; Read the next data byte from the synchronous serial port into W.
btfss pir1, rcif ;serial port has an input byte available ?
goto $-1 ;no, go back and check again
movf rcreg, w ;get the data byte into W
;--- +3 cycles, 20 total ---
; Write the byte in W to the external RAM. The address latches are
; already set to the right address.
movwf d0_reg ;write the data byte to the data bus
bcf memwr_pin ;write the data bus value to the RAM
goto wr_loop ;done with this byte, back to do next
;--- +5 cycles, 25 total ---
; End of main loop for the normal case.
; The low byte of the current RAM address was incremented, and the
; result was 0. This means there is a carry to the next byte.
; This section of code is implemented as a subroutine. It takes the
; same number of cycles (4) to GOTO a section of code then GOTO back to
; a known label as it does to CALL the code and RETURN to the main
; This section also ends the INDEX pulse. All tracks start on multiples
; of 25,000 bytes, which is a multiple of 8. The INDEX pulse is
; started when the track wraps back to its start. This method guarantees
; that the INDEX pulse lasts at least 8 bytes (64uS) and could last as
; long as 256 bytes (about 2mS).
wr_carr dbankis gbankadr
bsf index_pin ;de-assert the INDEX line
incf reg1 ;propagate the carry from byte 0 to byte 1
skip_nz ;no carry into byte 2 ?
incf reg2 ;propagate the carry from byte 1 to byte 2
dbankif gbankadr ;restore banks assumed by calling routine
;--- +8 cycles once every 256 iterations ---
; The CCP1 interrupt flag is set, which indicates we just wrapped back
; to the start of the disk track. This section of code is implemented
; as a subroutine.
; This routine starts the INDEX pulse and resets the current RAM address
; to the start of the data for the track.
wr_wrap dbankis pir1
bcf pir1, ccp1if ;clear the track wrap flag
; Assert the INDEX line. This goes low to indicate the start
; of the track. On real floppies, this comes from detecting
; a small hole in the floppy once per rotation.
bcf index_pin ;start the index pulse
; Reset the current RAM byte address to the start address
; of the data for this track.
movf reg3, w ;copy byte 0
movf reg4, w ;copy byte 1
movf reg5, w ;copy byte 2
dbankif pir1 ;set bank assumed at jump target
;--- +12 cycles once every 25,000 iterations ---
part 3 35 bytes content-type:text/plain; charset="us-ascii"
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