Post by thread:[EE] Eagle hard question, who can answer ?

I need to design a TQFN-56 package with exposed (thermal) pad and a number of through holes on this exposed pad between layers 1 and 16. Drawing the TQFN is ok. Drawing the through metalised holes is ok using vias. But in the library can't coexist vias on rectangles or polygons without generating error in DRC when component is used. The exposed pad needs a large numbers of holes and open copper surfaces without termals (while the other power planes on layers 1, 2, 3 and 16 needs thermals). So, how can be done in library without using restrict tricks and multiple planes in the board ? greetings, Vasile

Vasile Surducan wrote: > I need to design a TQFN-56 package with exposed (thermal) pad and a > number of through holes on this exposed pad between layers 1 and 16. > Drawing the TQFN is ok. Drawing the through metalised holes is ok > using vias. But in the library can't coexist vias on rectangles or > polygons without generating error in DRC when component is used. > The exposed pad needs a large numbers of holes and open copper > surfaces without termals (while the other power planes on layers 1, 2, > 3 and 16 needs thermals). > So, how can be done in library without using restrict tricks and > multiple planes in the board ? I don't think there is an easy way to do this. You might be able to do something manually with drills and filled areas, but I don't think there is a way to avoid all the resulting DRC errors. ****************************************************************** Embed Inc, Littleton Massachusetts, (978) 742-9014. #1 PIC consultant in 2004 program year. http://www.embedinc.com/products

what about.....forget the thermal pad and via's as part of the library part. Instead, drop the via's with thermals where you want the pad to be, then do a copper pour over the top of these, where the pad wants to lay. I've done that with other packages (mentor), and worked well, and did a copper pour with eagle and it went right over the top of the thermal reliefs. Sorta a pain, but I am pretty sure most packages won't allow the via field to be in the middle of the library part itself. Vasile Surducan <spam_OUTpiclist9TakeThisOuTgmail.com> wrote: I need to design a TQFN-56 package with exposed (thermal) pad and a number of through holes on this exposed pad between layers 1 and 16. Drawing the TQFN is ok. Drawing the through metalised holes is ok using vias. But in the library can't coexist vias on rectangles or polygons without generating error in DRC when component is used. The exposed pad needs a large numbers of holes and open copper surfaces without termals (while the other power planes on layers 1, 2, 3 and 16 needs thermals). So, how can be done in library without using restrict tricks and multiple planes in the board ? greetings, Vasile