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PICList Thread
'[EE] Generating a quadrature clock.'
2019\05\24@162105 by David Van Horn

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I know I can do this with a 74xx74 chip, but the real estate is depressingly huge for such a simple function.

This application should fit in a 5 pin SOT package.  VCC, GND, Clkin, I and Q out.
Does anyone here know where I can find such a chip?

Max frequency is <5MHz, VCC would be 2.5V minimum, and 3.3V max.


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David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO  80301 USA
phone: 303-417-1345  x110
email: spam_OUTdavid.vanhornTakeThisOuTspambackcountryaccess.com<.....david.vanhornKILLspamspam@spam@backcountryaccess.com>

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2019\05\24@164838 by Isaac M. Bavaresco

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There exists the SN74LVC1G74 (probably HC and HCT too), which is a
single-gate version of the 74xx74. It has just 8 pins and is available in
space-saving packages.

Em sex, 24 de mai de 2019 17:23, David Van Horn <
david.vanhornspamKILLspambackcountryaccess.com> escreveu:

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2019\05\24@175941 by Bob Blick

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But to generate a 90 degree output with only one flip-flop would take extra logic, it would still use a lot of board space.

Best regards, Bob

________________________________________
From: piclist-bouncesspamspam_OUTmit.edu <@spam@piclist-bouncesKILLspamspammit.edu> on behalf of Isaac M. Bavaresco <KILLspamisaacbavarescoKILLspamspamgmail.com>
Sent: Friday, May 24, 2019 1:50 PM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Generating a quadrature clock.

There exists the SN74LVC1G74 (probably HC and HCT too), which is a
single-gate version of the 74xx74. It has just 8 pins and is available in
space-saving packages.

Em sex, 24 de mai de 2019 17:23, David Van Horn <
RemoveMEdavid.vanhornTakeThisOuTspambackcountryaccess.com> escreveu:

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2019\05\24@180201 by Jim

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6 pin PIC

Regards,

Jim

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2019\05\24@180552 by Jim

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6 pin PIC.  10F20x series.  SOT23-6


Regards,

Jim

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2019\05\24@180925 by Bob Blick

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part 1 593 bytes content-type:text/plain; charset="iso-8859-1" (decoded quoted-printable)

Attached is a typical way of generating 90 degree clocks with two '74 gates Bob ________________________________________ From: piclist-bouncesSTOPspamspamspam_OUTmit.edu <spamBeGonepiclist-bouncesSTOPspamspamEraseMEmit.edu> on behalf of Isaac M. Bavaresco <KILLspamisaacbavarescospamBeGonespamgmail.com> Sent: Friday, May 24, 2019 1:50 PM To: Microcontroller discussion list - Public. Subject: Re: [EE] Generating a quadrature clock. There exists the SN74LVC1G74 (probably HC and HCT too), which is a single-gate version of the 74xx74. It has just 8 pins and is available in space-saving packages.

part 2 32768 bytes content-type:image/gif; name="7474PhaseSplitter.gif" (decode)


part 3 197 bytes content-type:text/plain; name="ATT00001.txt"
(decoded base64)

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2019\05\24@180925 by mad.scientist.at.largen/a

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or any programmable logic device if you need higher frequency.

"We the People Dare to Create a More Perfect Union" <aclu.org>



May 24, 2019, 4:01 PM by EraseMEjimspamEraseMEjpes.com:

>
> 6 pin PIC
>
> Regards,
>
> Jim
>
>> ---{Original Message removed}

2019\05\24@181607 by Bob Blick

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Of course in my casual sloppy way I forgot to show that one of the flip-flops needs an inverted input clock.

________________________________________
From: Bob Blick <@spam@bobblick@spam@spamspam_OUToutlook.com>
Sent: Friday, May 24, 2019 3:09 PM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Generating a quadrature clock.

Attached is a typical way of generating 90 degree clocks with two '74 gates

Bob

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2019\05\24@182558 by Isaac M. Bavaresco

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Then use one SN74LVC74 in TSSOP package plus one single-gate inverter
SN74LVC04 in SOT-23-5 package.

Em sex, 24 de mai de 2019 19:18, Bob Blick <spamBeGonebobblickspamKILLspamoutlook.com> escreveu:

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2019\05\24@192817 by Dwayne Reid

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Hi there, David.

A couple of off-hand suggestions that may not be any good:

1) PIC10F322 - see if you can use the CLC to do most of the heavy lifting.  I don't have ready access to the datasheet right now but it is worth looking at.

2) Silego Greenpak - they have some really useful programmable chips that should easily do what you want.  And they are **Tiny**!

dwayne


At 02:20 PM 5/24/2019, David Van Horn wrote:
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Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
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2019\05\24@201635 by Jean-Paul Louis

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David,
Did you check TI Tiny logic in SOT23-5 74 type flip flops

Just a thought,
Jean-Paul
N1JPL

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2019\05\24@223013 by Dwayne Reid

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Hi there, David.

I had a look at the PIC10F322 datasheet - you might be able to make something work but I suspect not.  There is only a single CLC module, having a single flip-flop plus lots of input gating.

I had hoped that perhaps you could use Timer0 as the other flip-flop but there is a 2-cycle sync delay on the clock input.

Perhaps someone else has ideas.

dwayne


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Custom Electronics Design and Manufacturing

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2019\05\25@025719 by RussellMc

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It probably doesn't help, as I've never seen a package with a flip-flop and
an XNOR gate in it :-), but:

Use

1 x XOR with inverted output (XNOR)
1 x flip flop .

FF_clock = clock. Arrange flip flop to toggle on clock say leading edge.
XNOR_in_A = Clk
XNOR_in_B = FF_Q

Quadrature clocks = FF_Q, XNOR_Out

Freq_quadclocks = Clk/2

_______________

Brain suggests that a counter or shift register with suitable feedback taps
may work.
TBD.


                Russell


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2019\05\25@095307 by Jean-Paul Louis

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David, your frequency out will be F/4 with 74 D latch or F/2 if you use differential circuits. Last time I did one such circuit, I used a small PLD from Lattice, but those are now discontinued.
Jean-Paul N1JPL 

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 On Fri, May 24, 2019 at 4:23 PM, David Van Horn<TakeThisOuTdavid.vanhornspamspambackcountryaccess.com> wrote:   I know I can do this with a 74xx74 chip, but the real estate is depressingly huge for such a simple function.

This application should fit in a 5 pin SOT package.  VCC, GND, Clkin, I and Q out.
Does anyone here know where I can find such a chip?

Max frequency is <5MHz, VCC would be 2.5V minimum, and 3.3V max.


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO  80301 USA
phone: 303-417-1345  x110
email: david.vanhornEraseMEspambackcountryaccess.com<RemoveMEdavid.vanhornEraseMEspamspam_OUTbackcountryaccess.com>

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2019\05\25@114617 by AB Pearce - UKRI STFC

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Any method other than the divide by 4 assumes the input clock has 50% duty cycle.

The divide by 4 will give a true quadrature output with any duty cycle clock that has pulse widths that properly clock the flip flops.



{Original Message removed}

2019\05\28@073438 by David Van Horn

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I've been having fun with the Silego chip software. The help in their app SUCKS as I can't actually read it.  Small dim text partially transparent for some reason.

That said, I have worked out a design that meets almost all my needs.  I'll be working with them today to settle on one or two candidates.


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO  80301 USA
phone: 303-417-1345  x110
email: @spam@david.vanhornRemoveMEspamEraseMEbackcountryaccess.com 

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