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'[EE] Logic gate draw excessive current in undefine'
2019\08\29@170238 by Jason White

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Hello PIC List!

I have a design that uses the 74LVC1G332. I found that it draws about 45mA
when 2.2V is applied to all three inputs and does not even get hot. The
purpose of this gate is to square a very slow moving voltage, the threshold
voltage accuracy and stability is unimportant. Hysteresis is not required.

My application is space and power constrained. Is there a logic gate that
does not exhibit this behavior? (100uA in the undefined would be much more
acceptable than 45mA) Maybe a schmitt trigger would be designed to
accommodate this?

Otherwise I think I will be forced to use a comparator which would add two
(or three) resistors to the design for a reference voltage. A single
transistor solution would probably not be optimal due to the limited gain.


Thanks!
Jason White
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2019\08\29@174621 by Bob Blick

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Hi Jason,
Yes, I would suggest a schmitt trigger for any application where you have slow rise or fall times. Other wise you can have excessive power consumption and/or oscillation.
Best regards, Bob

________________________________________
From: spam_OUTpiclist-bouncesTakeThisOuTspammit.edu <.....piclist-bouncesKILLspamspam@spam@mit.edu> on behalf of Jason White Sent: Thursday, August 29, 2019 2:01 PM
To: Microcontroller discussion list - Public.
Subject: [EE] Logic gate draw excessive current in undefined region,    smallest replacement?

Hello PIC List!

I have a design that uses the 74LVC1G332. I found that it draws about 45mA
when 2.2V is applied to all three inputs and does not even get hot. The
purpose of this gate is to square a very slow moving voltage, the threshold
voltage accuracy and stability is unimportant. Hysteresis is not required.

My application is space and power constrained. Is there a logic gate that
does not exhibit this behavior? (100uA in the undefined would be much more
acceptable than 45mA) Maybe a schmitt trigger would be designed to
accommodate this?

Otherwise I think I will be forced to use a comparator which would add two
(or three) resistors to the design for a reference voltage. A single
transistor solution would probably not be optimal due to the limited gain.


Thanks!
Jason White


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2019\08\29@174853 by James Cameron

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TI mentions a bus-hold feature, but I'm not sure how available it is.

Implications of Slow or Floating CMOS Inputs, July 1994 to September
2016, SCBA004D

http://www.ti.com/lit/an/scba004d/scba004d.pdf

On Thu, Aug 29, 2019 at 05:01:44PM -0400, Jason White wrote:
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2019\08\29@174923 by Brent Brown

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Yes, Schmitt trigger designed for this, they don't draw excessive "crossover" current. Does add hysteresis, hopefully that's acceptable. Can get them in various 1 and 2 input configurations, not sure if i've seen a 3 input one.
-------- Original message --------From: Jason White <whitewaterssoftwareinfospamKILLspamgmail.com> Date: 8/30/19  9:01 AM  (GMT+12:00) To: "Microcontroller discussion list - Public." <.....piclistKILLspamspam.....mit.edu> Subject: [EE] Logic gate draw excessive current in undefined region, smallest replacement? Hello PIC List!I have a design that uses the 74LVC1G332. I found that it draws about 45mAwhen 2.2V is applied to all three inputs and does not even get hot. Thepurpose of this gate is to square a very slow moving voltage, the thresholdvoltage accuracy and stability is unimportant. Hysteresis is not required.My application is space and power constrained. Is there a logic gate thatdoes not exhibit this behavior? (100uA in the undefined would be much moreacceptable than 45mA) Maybe a schmitt trigger would be designed toaccommodate this?Otherwise I think I will be forced to use a comparator which would add two(or three) resistors to the design for a reference voltage. A singletransistor solution would p!
robably not be optimal due to the limited gain.Thanks!Jason White-- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archiveView/change your membership options atmailman.mit.edu/mailman/listinfo/piclist
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2019\08\29@205221 by RussellMc

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On Fri, 30 Aug 2019 at 09:05, Jason White <EraseMEwhitewaterssoftwareinfospam_OUTspamTakeThisOuTgmail.com>
wrote:

> My application is space and power constrained. Is there a logic gate that

does not exhibit this behavior? (100uA in the undefined would be much more
acceptable than 45mA) Maybe a schmitt trigger would be designed to
>
>
> A Schmitt triggered gate is the obvious solution, as you and others have
noted.
Below I describe an extremely 'naughty' concept which may be able to be
made to work deep-ending on overall situation.
This arrangement

    - may not work at all
    - may be an utter disaster
    - may be able to be made to work extremely well

Odds are the naughtiness factor exceeds the levels acceptable in a real
world design :-).

"" Solution """: Add a 'suitably sized' resistor in the IC's Vdd line.

Greatly increased current drain will lower the IC's Vdd thus increasing the
relative voltage of the inputs relative to the IC.
Reduction of current drain will restore the voltages so there is a
potential for oscillation depending on time constants.

(This "works", if at all, on rising input waveforms.
A resistor in the Vss line will achieve a similar result with falling
inputs.
Both at once (probably) don't work for equal sized resistors. Assymetric
sizing may work in both directions in some cases but, by then magic is
probably safer).

I have never tried this with an IC.
But I have successfully added hysteresis in a transistor based circuit by
adding a small resistor in a current path and using the small pedestal to
raise a switching voltage level elsewhere. Not a formal Schmitt per se. In
that case the solution was 'almost elegant' rather than 'naughty' and
produced superb results with astonishingly small levels of hysteresis for
the results achieved. (ie calculation suggested that the level that worked
was far smaller than would be expected to be effective.


Russell
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2019\08\29@211119 by Jason White

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Russell that is pretty clever, I am half tempted to give it a try on one of
my existing prototype boards just to see if it works. The next revision
will probably get Schmitt trigger ICs since this is (will be) a safety
sensitive application.


On Thursday, August 29, 2019, RussellMc <apptechnzspamspam_OUTgmail.com> wrote:

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2019\08\29@220338 by Richard Graziano

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If you put a scope on the circuit you may see that this chip is in
oscillation. Did you use bypass capacitors?  See if it is oscillating. That
would cause lager current draw.


On Thu, Aug 29, 2019 at 9:14 PM Jason White <
KILLspamwhitewaterssoftwareinfoKILLspamspamgmail.com> wrote:

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2019\08\30@070355 by Jason White

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No apparent oscillation on the output. It is byassed with a 100nf cap and
on a 4 layer PCB with dedicated power and ground planes.

On Thursday, August 29, 2019, Richard Graziano <TakeThisOuTatrscientific018EraseMEspamspam_OUTgmail.com>
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2019\08\30@082022 by mike brown

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That's really thinking outside the box Russell.  I never cease to be amazed
by the things you come up with.  Otoh, once the current draw goes back to
normal, couldn't this lead to oscillation as the input moves back to the
undefined behavior region?

On Thu, Aug 29, 2019, 20:03 RussellMc <RemoveMEapptechnzEraseMEspamEraseMEgmail.com> wrote:

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2019\08\31@014515 by RussellMc

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On Sat, 31 Aug 2019 at 00:23, mike brown <RemoveMEmikeTakeThisOuTspamspamn5qmg.com> wrote:

> That's really thinking outside the box Russell.  I never cease to be amazed
> by the things you come up with.


Some of them even work :-).*

Otoh, once the current draw goes back to
normal, couldn't this lead to oscillation as the input moves back to the
undefined behavior region?

Yes indeed. As per my comment.


> > Reduction of current drain will restore the voltages so there is a
> potential for oscillation depending on time constants.


BUT, the switching changes the configuration into a new state which may or
may not have the same high drain.
Low to high and high to low transistions have different Vin/Icc maps and it
may be (and may not) that something can be made to work.
As noted, it's a "naughty" enough idea that some work will be required to
see if it can be formalised to an extent that is acceptable as a "proper"
design.


           Russell
* Satisfaction and sorrow occurs when I see others implement independently
an idea that I've thought of previously - occasionally years before. This
proves that the idea was viable - but also means that I missed a chance,
had I cared enough :-) .

One such I am quite pleased with is the concept for a rocket-propellant
pump (very simple and obvious) that would very greatly reduce the cost of
rocket engine development in certain classes of engine. The overwhelmingly
major portion of a new engine design is the turbo-pump development. This is
almost all of the cost and they tend not to be transferable between designs
with any degree of significant difference.  The concept elimnates the
turbopump and replaces it with a stunningly obvious alternative. My "input"
was only a paragraph or two of description on a rocketry list with none of
the hard work of actually trying it. It turned out that others on the list
(Flometrics ltd) were working on exactly my "public domained' suggestion
and were horrified at my having suggested it. Better still, Lockheed Martin
had applied for a patent about 3 years before that but at that stage this
was not known publicly:-). The horrified ones now have a NASA contract to
develop demonstration motors. Lockheed Martin seems to have overlooked the
potential :-).

Flometrics 2010 report on their "Pistonless pump". you'll not find my name
in there :-)


www.flometrics.com/wp-content/uploads/2014/09/AIAA-2010-7131-314.pdf
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