I'm working on a very low power application where we need a few more IO pins
than what we can get on the microcontroller and the project lead is
recommending this. It's basically an I2C addressable shift register, but it
claims to allow any pin to be an output OR an input without having to set
any direction bits. (!!!)
I can't get my head around how it can have pins that are inputs, and others
that are outputs without any direction registers in it. As far as I can see,
it drives any pin that you write out a 1 to with 1mA to the Vcc rail. So
they are fairly easy to overcome with an input that may need to drive that
pin low. Sort of the standard open collector with a pull up deal. No problem
so far.
But then they have something called IOHT that drives any pin that set high
hard to Vcc until after the last clock.
"An additional strong pull-up to VCC (IOHT) allows fast rising edges into
heavily loaded outputs. This device turns on when an output is written high
and is switched off by the negative edge of SCL"
So what are we saying? That its ok for some other device that is trying to
drive a low into one of these pins to drive against the supply rail as long
as you only do it for a little while?
His statement is that this will require less power over all than will any
standard available shift registers. Isn't even the 1mA pull up going to suck
down the juice for any input that happens to be a zero? Not to mention the
ton of juice whenever we write out new values to the output pins and that
zero gets driven high at full power for the time between the bit and the
last clock?
Am I missing something here?
I've been looking for a set of good low power shift registers (one in and
one out), and I have to admit, I can't find anything that will pull less
than about 100uA in normal operation (not including what ever it is driving
as an output). This PDF 8575 has an Icc of 75uA or less in operating mode
and will standby down to around 3uA.
James,
I think that if you set them high & then use them as inputs you are
OK. If you only read from them then the high current pulse output is
not enabled. The only time it is enabled is if you are writing to them
as outputs and are going through a low-high transistion.
"An additional strong pullup to V CC (I OHT ) allows fast rising edges
into heavily loaded outputs. This device turns on when an output is
written high and is switched off by the
negative edge of SCL. The I/Os should be high before being used as
inputs. After power on, as all the I/Os are
set high, all of them can be used as inputs. Any change in setting of
the I/Os as either input or outputs can be
done with the write mode. If a high is applied externally to an I/O
that has been written earlier to low, a large
current (I OL ) will flow to GND."
> Has anybody used this TI PDF 8575 chip?
>
> http://focus.ti.com/lit/ds/symlink/pcf8575.pdf
>
> I'm working on a very low power application where we need a few more IO pins
> than what we can get on the microcontroller and the project lead is
> recommending this. It's basically an I2C addressable shift register, but it
> claims to allow any pin to be an output OR an input without having to set
> any direction bits. (!!!)
>
> I can't get my head around how it can have pins that are inputs, and others
> that are outputs without any direction registers in it. As far as I can see,
> it drives any pin that you write out a 1 to with 1mA to the Vcc rail. So
> they are fairly easy to overcome with an input that may need to drive that
> pin low. Sort of the standard open collector with a pull up deal. No problem
> so far.
>
> But then they have something called IOHT that drives any pin that set high
> hard to Vcc until after the last clock.
>
> "An additional strong pull-up to VCC (IOHT) allows fast rising edges into
> heavily loaded outputs. This device turns on when an output is written high
> and is switched off by the negative edge of SCL"
>
> So what are we saying? That its ok for some other device that is trying to
> drive a low into one of these pins to drive against the supply rail as long
> as you only do it for a little while?
>
> His statement is that this will require less power over all than will any
> standard available shift registers. Isn't even the 1mA pull up going to suck
> down the juice for any input that happens to be a zero? Not to mention the
> ton of juice whenever we write out new values to the output pins and that
> zero gets driven high at full power for the time between the bit and the
> last clock?
>
> Am I missing something here?
>
> I've been looking for a set of good low power shift registers (one in and
> one out), and I have to admit, I can't find anything that will pull less
> than about 100uA in normal operation (not including what ever it is driving
> as an output). This PDF 8575 has an Icc of 75uA or less in operating mode
> and will standby down to around 3uA.
>
> Help?
>
> ---
> James Newton: PICList webmaster/Admin
> jamesnewtonKILLspampiclist.com 1-619-652-0593 phone
> http://www.piclist.com/member/JMN-EFP-786
> PIC/PICList FAQ: http://www.piclist.com
>
>
> "An additional strong pull-up to VCC (IOHT) allows fast rising edges
> into heavily loaded outputs. This device turns on when an output is
> written high and is switched off by the negative edge of SCL"
>
> So what are we saying? That its ok for some other device that is trying
> to drive a low into one of these pins to drive against the supply rail
> as long as you only do it for a little while?
>
> http://focus.ti.com/lit/ds/symlink/pcf8575.pdf
Hi James,
Looks like the standard 8051 micro style quasi-bidirectional I/O structure.
They too (at least some, possibly all) have a "stronger" pullup that briefly
kicks in during the output transition from 0 to 1. Help overcome line
capacitance to square up 0 to 1 edges while maintaining low current static
operation. Presumably TI is a second source for this originally Phillips
design?
On page 10 of the data sheet for the TI PCF8575 (is that PDF or PCF? -
data sheet says PCF) it indicates max of 300uA "standard" pullup current
and typ 1mA transient pullup current. So, yes it is ok to have some other
device driving a 0 into one of these inputs even if you try to output a 1 at the
same time (but why would would you?).
Power consumption will of course depend on the state of the inputs as you
suggest, which of course is always the drawback of this I/O design.
--
Brent Brown, Electronic Design Solutions
16 English Street, Hamilton 2001, New Zealand
Ph: +64 7 849 0069
Fax: +64 7 849 0071
Cell/txt: 027 433 4069
eMail: .....brent.brownKILLspam.....clear.net.nz
At 01:41 PM 11/1/2005 -0800, you wrote:
>Has anybody used this TI PDF 8575 chip?
>
>http://focus.ti.com/lit/ds/symlink/pcf8575.pdf
>
>I'm working on a very low power application where we need a few more IO pins
>than what we can get on the microcontroller and the project lead is
>recommending this. It's basically an I2C addressable shift register, but it
>claims to allow any pin to be an output OR an input without having to set
>any direction bits. (!!!)
>
>I can't get my head around how it can have pins that are inputs, and others
>that are outputs without any direction registers in it. As far as I can see,
>it drives any pin that you write out a 1 to with 1mA to the Vcc rail. So
I see 100uA, with a pretty huge tolerance (~3:1 in either direction)
>they are fairly easy to overcome with an input that may need to drive that
>pin low. Sort of the standard open collector with a pull up deal. No problem
>so far.
>
>But then they have something called IOHT that drives any pin that set high
>hard to Vcc until after the last clock.
>
>"An additional strong pull-up to VCC (IOHT) allows fast rising edges into
>heavily loaded outputs. This device turns on when an output is written high
>and is switched off by the negative edge of SCL"
>
>So what are we saying? That its ok for some other device that is trying to
>drive a low into one of these pins to drive against the supply rail as long
>as you only do it for a little while?
Yes, this is in the form of the *execrable* (IMHO) psuedo-bidirectional I/O of
the original 8051.
>His statement is that this will require less power over all than will any
>standard available shift registers. Isn't even the 1mA pull up going to suck
>down the juice for any input that happens to be a zero?
Yes, indeed, though I think it's 100uA. Note also that the CMOS input draws
extra current (200uA per unit) if the input isn't very close to one rail or
the other. That's normal with CMOS, of course.
>Not to mention the
>ton of juice whenever we write out new values to the output pins and that
>zero gets driven high at full power for the time between the bit and the
>last clock?
That won't amount to much, since it's for such a short time, and it's only
1mA total per input typical (No maximum).
>Am I missing something here?
>
>I've been looking for a set of good low power shift registers (one in and
>one out), and I have to admit, I can't find anything that will pull less
>than about 100uA in normal operation (not including what ever it is driving
>as an output). This PDF 8575 has an Icc of 75uA or less in operating mode
>and will standby down to around 3uA.
>
>Help?
Why can't you just use regular garden variety CMOS (HC or LVC) logic and an
SPI port (hardware or bit-banged)? Cheap & easily available, now and 5
years from now.
74HC595, for example, even at full temperature and 6V Vcc is rated for 80uA
maximum. It will be much less typically. The 74LV595 is 20uA maximum at 5.4V
over temperature. It will be much less typically.
I really hate specifying single-sourced stuff if there's any reasonable
way around it.
>Power consumption will of course depend on the state of the inputs as you
>suggest, which of course is always the drawback of this I/O design.
I guess if you only need to read them infrequently, you could output all
1's to the inputs, read the inputs, then output all zeros real quick
like, and wait for (long time) until the next read. That could save most
of the pullup power.
Richard Prosser wrote:
> I think that if you set them high & then use them as inputs you are
> OK. If you only read from them then the high current pulse output is
> not enabled. The only time it is enabled is if you are writing to them
> as outputs and are going through a low-high transistion.
>
> "An additional strong pullup to V CC (I OHT ) allows fast rising edges
> into heavily loaded outputs. This device turns on when an output is
> written high and is switched off by the
> negative edge of SCL. The I/Os should be high before being used as
> inputs. After power on, as all the I/Os are
> set high, all of them can be used as inputs. Any change in setting of
> the I/Os as either input or outputs can be
> done with the write mode. If a high is applied externally to an I/O
> that has been written earlier to low, a large
> current (I OL ) will flow to GND."
That explains how it can be used as inputs without fighting the temporary
strong pullup, but I still don't see how this can be "low power" when all
inputs are driven low externally.
******************************************************************
Embed Inc, Littleton Massachusetts, (978) 742-9014. #1 PIC
consultant in 2004 program year. http://www.embedinc.com/products
Spehro Pefhany wrote:
> I guess if you only need to read them infrequently, you could output
> all 1's to the inputs, read the inputs, then output all zeros real
> quick
> like, and wait for (long time) until the next read. That could save
> most
> of the pullup power.
That would be very bad when the inputs are actively driven high. Unlike the
pullups on this chip, the pulldowns are capable of relatively large
currents.
******************************************************************
Embed Inc, Littleton Massachusetts, (978) 742-9014. #1 PIC
consultant in 2004 program year. http://www.embedinc.com/products
> I think that if you set them high & then use them as inputs
> you are OK. If you only read from them then the high current
> pulse output is not enabled. The only time it is enabled is
> if you are writing to them as outputs and are going through a
> low-high transistion.
Right, but how does one avoid writing a 1 to the pins you are using as
inputs while at the exact same time writing 1's or 0's to the other pins
which you are using as outputs?
> On page 10 of the data sheet for the TI PCF8575 (is that PDF
> or PCF? - data sheet says PCF) it indicates max of 300uA
> "standard" pullup current and typ 1mA transient pullup
> current. So, yes it is ok to have some other device driving a
> 0 into one of these inputs even if you try to output a 1 at
> the same time (but why would would you?).
Because you have no other option when you need to put others pins (used for
outputs) into new states. Or did I miss something?
That could be a problem. I was thinking you would either be reading
bits or writing them - i.e all port pins would be of the same "type".
But if you need to read some & write others on the same device then I
guess you have to put up with a momentary higher current - although if
it's limited to 1mA as others suggest then that's not too much a
penalty.
RP
> > I think that if you set them high & then use them as inputs
> > you are OK. If you only read from them then the high current
> > pulse output is not enabled. The only time it is enabled is
> > if you are writing to them as outputs and are going through a
> > low-high transistion.
>
> Right, but how does one avoid writing a 1 to the pins you are using as
> inputs while at the exact same time writing 1's or 0's to the other pins
> which you are using as outputs?
>
> > >
> > > http://focus.ti.com/lit/ds/symlink/pcf8575.pdf
> > >
>
> ---
> James Newton: PICList webmaster/Admin
> spamBeGonejamesnewtonspamBeGonepiclist.com 1-619-652-0593 phone
> http://www.piclist.com/member/JMN-EFP-786
> PIC/PICList FAQ: http://www.piclist.com
>
>
> >as I can see, it drives any pin that you write out a 1 to
> with 1mA to
> >the Vcc rail. So
>
> I see 100uA, with a pretty huge tolerance (~3:1 in either direction)
>
> Why can't you just use regular garden variety CMOS (HC or
> LVC) logic and an SPI port (hardware or bit-banged)? Cheap &
> easily available, now and 5 years from now.
>
> 74HC595, for example, even at full temperature and 6V Vcc is
> rated for 80uA maximum. It will be much less typically. The
> 74LV595 is 20uA maximum at 5.4V over temperature. It will be
> much less typically.
>
> I really hate specifying single-sourced stuff if there's any
> reasonable way around it.
Oh so true! But the real problem is the input device (a parallel load,
serial out)
The 74x323 is the normal thing I have used before, but I can't find it in
LC/LV/HC etc... I found LS in stock at rocelec.com but they want to quote
so I don't know the price.
I haven't used the 74x165 but it looks like the same thing? I can find it in
the LV family for under a buck from many sources http://www.findchips.com/avail?part=74LV165
- - Specs: Icc: < 20uA Vcc: 2v < 6v
rocky.digikey.com/WebLib/Texas%20Instruments/Web%20data/SN74LV165A.pd
f
So we should go with that right? Why didn't the hardware guy suggest it?
Which looks perfect to me... Any reason why I shouldn't recommend that?
It's really freaking me out that these options were bypassed for that weird
pseudo input and output at the same time chip. I'm not a hardware expert so
I have to be really sure of myself before I say anything.
The only thing I can see that makes a difference is that it is I2C
addressable so we could expand to 16 or more IO without any additional uC
pins (but you can stack on shift registers for that) and that it doesn't
need extra pins for the input vice the output side.
So what is the minimum number of micro pins to hook up 8+ bits of input AND
output via shift registers? E.g. one parallel input shift out and one shift
in parallel out. They can share the clock, but not latch and data so that is
5 lines, but there should be some clever way to reduce that count.
I also seem to remember people putting a RC from the clock to the latch so
that it would trigger a leading edge latch when the clock had been inactive
for a bit?
Just for reference: I guess these are the "usual suspects" for this sort of
thing?
74x165 8-bit parallel load, shift out.
74x323 8-bit shift register with output and parallel load.
Can't latch the existing output while loading a new one. But it works great
for input since it can parallel load and shift out. As long as your output
can "wiggle" during loads, this one chip can be configured as an input or
output. (not both at once)
74x595 8-bit shift register with output latch
Shift a new set in, then dump it to the outputs. Perfect for output.
HC $0.14, no LC, LS $4<$7, LV ~$0.40 (no stock)
74x673 16-bit, shift and parallel latch or load.
Perfect! Can be input or output (not both at once)
Just a BIT expensive (F is $6<$24 EACH, LS $26<$56, no HC, no LV, etc...)
At 06:32 PM 11/1/2005 -0500, you wrote:
>Spehro Pefhany wrote:
> > I guess if you only need to read them infrequently, you could output
> > all 1's to the inputs, read the inputs, then output all zeros real
> > quick
> > like, and wait for (long time) until the next read. That could save
> > most
> > of the pullup power.
>
>That would be very bad when the inputs are actively driven high. Unlike the
>pullups on this chip, the pulldowns are capable of relatively large
>currents.
Yes, you'd want to drive them with open-drain, open-collector, or a switch
to ground to use that method.
>I haven't used the 74x165 but it looks like the same thing? I can find it in
>the LV family for under a buck from many sources
>http://www.findchips.com/avail?part=74LV165
>- - Specs: Icc: < 20uA Vcc: 2v < 6v
>rocky.digikey.com/WebLib/Texas%20Instruments/Web%20data/SN74LV165A.pd
>f
>
>So we should go with that right? Why didn't the hardware guy suggest it?
I would think so. Why? Not enough information to know. Perhaps he thinks
there's a problem with the total number of pins to drive it, perhaps the
I2C bus is used elsewhere, perhaps he's a young designer who looks for
a custom "chip" solution for every problem.
>It's really freaking me out that these options were bypassed for that weird
>pseudo input and output at the same time chip. I'm not a hardware expert so
>I have to be really sure of myself before I say anything.
>
>The only thing I can see that makes a difference is that it is I2C
>addressable so we could expand to 16 or more IO without any additional uC
>pins (but you can stack on shift registers for that) and that it doesn't
>need extra pins for the input vice the output side.
>So what is the minimum number of micro pins to hook up 8+ bits of input AND
>output via shift registers? E.g. one parallel input shift out and one shift
>in parallel out. They can share the clock, but not latch and data so that is
>5 lines, but there should be some clever way to reduce that count.
The most obvious way would use 5 pins no parts (and could use the hardware
SPI).
I'll let someone else think about the implications of sharing various
pins and meeting your implicit specification of zero quiescent power draw.
I'm guessing an inverter and an RC network would knock it down to 3 pins,
and it could be knocked down to two as you suggest below, either with an
RC or with a retriggerable monostable.
But if you're gaining 16, maybe you can spend 5 on driving them cleanly
and fast with zero power. It would only take microseconds to swap the input
and output bytes with a h/w SPI.
>I also seem to remember people putting a RC from the clock to the latch so
>that it would trigger a leading edge latch when the clock had been inactive
>for a bit?
As so.
>Just for reference: I guess these are the "usual suspects" for this sort of
>thing?
>
>74x165 8-bit parallel load, shift out.
>
>74x595 8-bit shift register with output latch
>Shift a new set in, then dump it to the outputs. Perfect for output.
>HC $0.14
> That explains how it can be used as inputs without fighting the temporary
> strong pullup, but I still don't see how this can be "low power" when all
> inputs are driven low externally.
That is a part of the standard MCS51 IO scheme. The weak pullup is not
driven high directly it is driven by a schmitt trigger which senses the
actual pin voltage. So if an external load manages to pull the pin low
below Vil for the schmitt the pullup turns off and the pin stays low. An
external pullup or high drive is needed to pull it up above Vih after
which the schmitt toggles high and helps with the weak pullup. When a 1
is output then the strong pullup (1.6mA?) is tuned on for two clock
cycles (on the CPU) and if it can fight the external load (i.e. the pin
is not held low) then the pin will assume the high state again.
It is a slightly strange scheme that causes many people headaches until
they get to work with it smoothly. In most non-low power applications an
external pullup is provided by the user and the scheme is ignored.
The scheme really shines when such IOs are connected to similar IOs
(f.ex. MCS51 pin to another MCS51 pin - presumably on another chip).
Then the line is bidirectional and minimum power consumption is achieved
at all times.
The internal structure of the MCS51 IO pin is described in the MCS51
device family hardware data sheets.
>> I think that if you set them high & then use them as inputs
>> you are OK. If you only read from them then the high current
>> pulse output is not enabled. The only time it is enabled is
>> if you are writing to them as outputs and are going through a
>> low-high transistion.
>
> Right, but how does one avoid writing a 1 to the pins you are using as
> inputs while at the exact same time writing 1's or 0's to the other pins
> which you are using as outputs?
You do write 1s to the pins used as inputs, during their being read.
Then you write them back as zeros.
be Mi an input mask (1s for any input bits) and Ro an output shadow
register (has 0 or 1 for any output bits and 0s for any input bits),
then:
read_inputs:
Sdata = Mi | Ro
write_i2c Sdata ; turn on inputs which are not held low
Temp = read_i2c & Mi ; inputs only
write_i2c Ro ; turn off input pullups
return
All data is on 16 bits in this scheme.
The internal schematic of the 8575 does not seem to reflect the Schmitt
scheme I wrote about but I think I am right about it. Maybe this variant
does not have the schmitt scheme.
> So what is the minimum number of micro pins to hook up 8+ bits of input AND
> output via shift registers? E.g. one parallel input shift out and one shift
> in parallel out. They can share the clock, but not latch and data so that is
> 5 lines, but there should be some clever way to reduce that count.
If you can afford the extra time simply daisy chain input and output
registers (not necessarily grouped). Minimum to drive is 1 clock/strobe
and 2 data IO pins (1O 1I). This requires the dodgy RC strobe derivation
from clock gaps. Add one more pin for proper strobe and it's 4 pins.
Imho by the time you need a lot of IO it may make sense to use another
low cost PIC for that, as slave, on RC clock.
I prefer CD4094 + CD4021 for this sort of application. Voltage range is
3 to 15V ;-) It's only the good stuff they don't make anymore (or so
they say - I think that these chips will be around forever).
> I prefer CD4094 + CD4021 for this sort of application. Voltage range
> is 3 to 15V ;-) It's only the good stuff they don't make anymore (or
> so they say - I think that these chips will be around forever).
>
> Peter
>
I like the LV595 if below 5V and HC595 if 5V. The advantage is that these
chips are VERY gutsy, can deliver 25mA ea at either rail all day long.
At 12:29 PM 11/2/2005 -0700, you wrote:
>Peter wrote:
>
>>I prefer CD4094 + CD4021 for this sort of application. Voltage range is 3
>>to 15V ;-) It's only the good stuff they don't make anymore (or so they
>>say - I think that these chips will be around forever).
>>
>>Peter
>I like the LV595 if below 5V and HC595 if 5V. The advantage is that these
>chips are VERY gutsy, can deliver 25mA ea at either rail all day long.
>
>--Bob
Yes, abs. max. is 35mA on the Qn outputs, but it's pretty easy to exceed
the maximum Icc or Ignd rating of 70mA. 8-(
> At 12:29 PM 11/2/2005 -0700, you wrote:
>
>> Peter wrote:
>>
>>> I prefer CD4094 + CD4021 for this sort of application. Voltage range
>>> is 3 to 15V ;-) It's only the good stuff they don't make anymore (or
>>> so they say - I think that these chips will be around forever).
>>>
>>> Peter
>>
>> I like the LV595 if below 5V and HC595 if 5V. The advantage is that
>> these
>> chips are VERY gutsy, can deliver 25mA ea at either rail all day long.
>>
>> --Bob
>
>
> Yes, abs. max. is 35mA on the Qn outputs, but it's pretty easy to exceed
> the maximum Icc or Ignd rating of 70mA. 8-(
>
Rarely are more than one or two outputs driving that hard at the same
time, unless
you are driving LED arrays. I've never run into a problem with
overheating. Most of
my designs have one or two external 25mA source/sinks, then the rest of
the device
is simple logic controls.
>Spehro Pefhany wrote:
>
>>At 12:29 PM 11/2/2005 -0700, you wrote:
>>
>>>Peter wrote:
>>>
>>>>I prefer CD4094 + CD4021 for this sort of application. Voltage range is
>>>>3 to 15V ;-) It's only the good stuff they don't make anymore (or so
>>>>they say - I think that these chips will be around forever).
>>>>
>>>>Peter
>>>
>>>I like the LV595 if below 5V and HC595 if 5V. The advantage is that these
>>>chips are VERY gutsy, can deliver 25mA ea at either rail all day long.
>>>
>>>--Bob
>>
>>
>>Yes, abs. max. is 35mA on the Qn outputs, but it's pretty easy to exceed
>>the maximum Icc or Ignd rating of 70mA. 8-(
>Rarely are more than one or two outputs driving that hard at the same
>time, unless
>you are driving LED arrays. I've never run into a problem with
>overheating. Most of
>my designs have one or two external 25mA source/sinks, then the rest of
>the device
>is simple logic controls.
>
>--Bob
Bob, I'm worried about more subtle failure modes such as metal migration. I
agree that overheating is not an issue. And LED arrays is something I deal
with frequently.
On 11/1/05, Spehro Pefhany <RemoveMEspeffKILLspaminterlog.com> wrote:
> At 05:32 PM 11/1/2005 -0800, you wrote:
> >I also seem to remember people putting a RC from the clock to the latch so
> >that it would trigger a leading edge latch when the clock had been inactive
> >for a bit?
>
> As so.
>
But watch the rise/fall time requirements on that latch input.
Regards,
Mark
markrages@gmail
--
You think that it is a secret, but it never has been one.
- fortune cookie
> So what is the minimum number of micro pins to
> hook up 8+ bits of input AND output via shift
> registers? E.g. one parallel input shift out and
> one shift in parallel out. They can share the clock,
> but not latch and data so that is 5 lines, but there
> should be some clever way to reduce that count.
James,
Why not 28 pin PIC16F72 with I2C and SPI?
You can program it to handle data in virtually any way.
It eats 20 micro amp at 3V 32 kHz (You didn't specify
speed)
>
> James,
>
> Why not 28 pin PIC16F72 with I2C and SPI?
> You can program it to handle data in virtually any way.
> It eats 20 micro amp at 3V 32 kHz (You didn't specify
> speed)
>
That is most likely a much better suggestion and one that I had already
passed on. The noises that I hear when I say that are about not having a PIC
programmer available (but I do and I can write the code for it) and a lack
of human programmer time (but I have ready made code for it)
I think I've got them convinced to use the standard shift registers...
James Newton wrote:> > Why not 28 pin PIC16F72 with I2C and SPI?> > You can program it to handle data in virtually any way.> > It eats 20 micro amp at 3V 32 kHz (You didn't specify> > speed)> >> That is most likely a much better suggestion and one that I had already> passed on. The noises that I hear when I say that are about not having a PIC> programmer available (but I do and I can write the code for it) and a lack> of human programmer time (but I have ready made code for it)>> I think I've got them convinced to use the standard shift registers...
Microchip has cheap almost standard I2C registers (based on PIC16F72,I'd suggest):
MCP23016 16-Bit I2C™ I/O Expander.
Mike
piclist.com 1-619-652-0593 phone
