Post by thread:[OT] 4MBit DRAM

A slightly off-topic question here but does anyone know of a 4Mbit DRAM that has a single column strobe instead of the usual two ? Sorry for the OT'ness but I need something quickly and a search of the usual suspects (manufacturers) has been fruitless. Regards... _________________________________________________________________ Dave Duffy. Audio Visual Devices E-mail: spam_OUTAVDTakeThisOuTmailbox.uq.edu.au Phone: +61 7 38210362 Facsimile: +61 7 38210281 Unit 8, 9-11 Trade Street, Cleveland, Queensland 4163 Australia _________________________________________________________________

Eh?. DRAM has a row address strobe and a column address strobe so as to cut down on package pins. I've never heard of a DRAM with a single address strobe; the pincount would be quite substantial. {Quote hidden}> ---------- > From: David Duffy[SMTP:.....AVDKILLspam@spam@MAILBOX.UQ.EDU.AU] > Reply To: pic microcontroller discussion list > Sent: Wednesday, December 03, 1997 10:16 PM > To: PICLISTKILLspamMITVMA.MIT.EDU > Subject: [OT] 4MBit DRAM > > A slightly off-topic question here but does anyone know of a 4Mbit > DRAM that has a single column strobe instead of the usual two ? > Sorry for the OT'ness but I need something quickly and a search > of the usual suspects (manufacturers) has been fruitless. > Regards... > _________________________________________________________________ > Dave Duffy. Audio Visual Devices E-mail: .....AVDKILLspam.....mailbox.uq.edu.au > Phone: +61 7 38210362 Facsimile: +61 7 38210281 > Unit 8, 9-11 Trade Street, Cleveland, Queensland 4163 Australia > _________________________________________________________________ >

No.No. What I mean is only one CAS pin. (COLUMN address strobe) That is; RAS + CAS (2 pins) not RAS + UCAS + LCAS (3 pins) >Eh?. DRAM has a row address strobe and a column address strobe so as to >cut down on package pins. I've never heard of a DRAM with a single >address strobe; the pincount would be quite substantial. > >> A slightly off-topic question here but does anyone know of a 4Mbit >> DRAM that has a single column strobe instead of the usual two ? >> Sorry for the OT'ness but I need something quickly and a search >> of the usual suspects (manufacturers) has been fruitless. _________________________________________________________________ Dave Duffy. Audio Visual Devices E-mail: EraseMEAVDspam_OUTTakeThisOuTmailbox.uq.edu.au Phone: +61 7 38210362 Facsimile: +61 7 38210281 Unit 8, 9-11 Trade Street, Cleveland, Queensland 4163 Australia _________________________________________________________________

Hi, > A slightly off-topic question here but does anyone know of a 4Mbit > DRAM that has a single column strobe instead of the usual two ? > Sorry for the OT'ness but I need something quickly and a search > of the usual suspects (manufacturers) has been fruitless. > Regards... I don't think there are any. I presume the DRAM is organized as 512Kx8. 512K = 2^19 and 19/2 is not an integer. Since the RAM is organized in a square matrix (on all DRAM's I know of), the 512Kx8 will be organized as two 2^9 by 2^9 matrixes. The two CAS lines select between the two matrixes. An 8MBit DRAM will again have only one CAS line since it would organized as one 2^10 by 2^10 matrix - giving 1024Kx8. Anyway, that's the way I think it is ;-) Niki

> A slightly off-topic question here but does anyone know of a 4Mbit > DRAM that has a single column strobe instead of the usual two ? > Sorry for the OT'ness but I need something quickly and a search > of the usual suspects (manufacturers) has been fruitless. > Regards... In the 1996 Samsung DRAM data book, I found some 4M x 1 bit parts. It looks like these parts are available in SOJ and TSOP package. KM41C4000C/CL (5V) KM41V4000C/CL (3.3V) available in 50 to 80ns speeds Most other DRAM manufacturers have stopped making the 'by 1' parts, since modern CPU's have such wide data busses. The 4M x 1 parts will not be available much longer. Dave

David Duffy <AVDspam_OUTMAILBOX.UQ.EDU.AU> wrote: > A slightly off-topic question here but does anyone know of a 4Mbit > DRAM that has a single column strobe instead of the usual two ? and later: > No.No. What I mean is only one CAS pin. (COLUMN address strobe) > That is; RAS + CAS (2 pins) not RAS + UCAS + LCAS (3 pins) Sounds to me like you're talking about a 256K*16 part with separate CAS strobes for two eight-bit sections. If that is the case, why not just tie UCAS and LCAS together? AFAIK, all the 16-bit-wide parts have either two CAS strobes, or two Write Enable lines, in order to allow single-byte writes. DRAM typically offers two variants of the write cycle, early write and late write. These are distinguished by whether the write enable is asserted early or late in the cycle. Some microprocessors do not give a write indication or byte selects until late in the memory cycle, in which case it is easiest to use the dual-write-enable DRAMs. Otherwise, the dual-CAS DRAMs are typically used. With either style of DRAM, if you don't need independent byte control, you can simply tie the paired signals together. Cheers, Eric