Post by thread:[OT] using PIC 4 sync processing: TV sync separato

You could as well check this one out. Mine, no adjustments, 5 Vdc operation, ultra low current, looks good but never yet used in commercial projects, requires low Z video source (tapping a video buffer before the O/P cap. is ok and supplies the DC bias too): +----+--------+---O + 5V |+ / / --- \ \ --- / / | | | +----+- A +- B | | \ - / V 1N60 \ - | | | /v | /v Video 1Vpp O------------|<-------------|< + 1.8 V dc | \ | \ bias | | === === 2 x PNP medium freq. low power Points A and B are fed to the (-) and resp. (+) inputs of a half of a LM393 comparator. The output of the comparator has a 10 kOhm pull-up and is fed to whatever you need, such as a PIC. The inputs A and B can be swapped to invert the polarity of the output, which is composite sync at CMOS level (also suits TTL, and HLL as the comparator can be powered from higher voltage). The second half of the 393 can be used to strip VD from the output if required. The key part is the 1N60 which is a Ge or hot carrier diode, with a voltage drop under 0.22 V on it when open. The circuit has no output when there is no input signal, and the output state is defined, as long as the bias is present. It also won't react to signals and noise < 0.2 Vpp supplied instead of video, also not to tuner noise, if below this peak value. If changing the bias, beware the CMMR of the 339 which does not include Vcc. Opinions are welcome (I've built this circuit and tested it under various conditions, but that's not much). Peter

Peter L. Peres wrote: {Quote hidden}> You could as well check this one out. Mine, no adjustments, 5 Vdc > operation, ultra low current, looks good but never yet used in commercial > projects, requires low Z video source (tapping a video buffer before the > O/P cap. is ok and supplies the DC bias too): > > +----+--------+---O + 5V > |+ / / > --- \ \ > --- / / > | | | > +----+- A +- B > | | > \ - > / V 1N60 > \ - > | | > | /v | /v > Video 1Vpp O------------|<-------------|< > + 1.8 V dc | \ | \ > bias | | > === === > > 2 x PNP medium freq. low power > > Points A and B are fed to the (-) and resp. (+) inputs of a half of a > LM393 comparator. The output of the comparator has a 10 kOhm pull-up and > is fed to whatever you need, such as a PIC. The inputs A and B can be > swapped to invert the polarity of the output, which is composite sync at > CMOS level (also suits TTL, and HLL as the comparator can be powered > from higher voltage). The second half of the 393 can be used to strip VD > from the output if required. The key part is the 1N60 which is a Ge or hot > carrier diode, with a voltage drop under 0.22 V on it when open. > > The circuit has no output when there is no input signal, and the output > state is defined, as long as the bias is present. It also won't react to > signals and noise < 0.2 Vpp supplied instead of video, also not to tuner > noise, if below this peak value. > > If changing the bias, beware the CMMR of the 339 which does not include > Vcc. > > Opinions are welcome (I've built this circuit and tested it under various > conditions, but that's not much). > > Peter If you were to use a pic, how would you separate the vertical sync from the horizontal sync? The vertical sync would be a positive going pulse as with all the others.How would the pic distinguish between the pulses? Dominic

On Sat, 25 Jul 1998, Dominic Gualtieri wrote: > If you were to use a pic, how would you separate the vertical sync from the > horizontal sync? The vertical sync would be a positive going pulse as with all > the others.How would > the pic distinguish between the pulses? > > Dominic By timing. Outside the V sync pulse the signal (assuming negative sync, as seen on a real video signal) is mostly '1', and inside it is mostly '0'. There are also other complications, called pre-equalization and post-equalization pulses. Get a TV standard description paper / textbook and look it up under 'interlaced frame scanning / timing'). As I have said before, synchronizing a PIC with a TV signal using a software loop only won't do for character generators/effects etc because at 4 MHz the best lock accuracy that can be expected is 1 usec, which is one order of magnitude worse than the maximum acceptable value. However, better sync can be obtained by using a LC oscillator, a varicap, a pin used in PWM output mode as D/A, and a lot of cunning code. This requires a lot of effort and is not worth your while. A 4046 PLL will do it much better for less money and 10 minutes of soldering. Its output can be used by a PIC. Peter