>> 1) If I use intrc can I still use the UART ???
>
> This is strictly a matter of timing tolerance between the two devices on the
> line.  The receiver looks for the leading edge of the start bit, then times
> the other bits relative to that.  At 8 data bits, the center of the last bit
> is 8 1/2 bits from the leading edge of the start bit.  The absolute maximum
> tolerable error is therefore 5.88%, which causes the last data bit to be
> sampled at its edge instead of the middle.  Most receivers sync everything
> to a 16x baud clock, so there is an additional small uncertainty in
> measuring the leading edge of the stop bit.  Of course, you don't want to be
> near the guaranteed to fail limit anyway.  I like to see no more than about
> 1/4 bit time error by the last bit, or about 3% clock mismatch betwen
> receiver and transmitter.
>
> Keep in mind that this is the combined error between receiver and
> transmitter.  If you know the other end is right on (like a PC, for
> example), then you can get away with 3% mismatch in the PIC.  If you've got
> two PICs with uncertain oscillators, then they each need to be within 1.5%.
>
>
> ********************************************************************
> Olin Lathrop, embedded systems consultant in Littleton Massachusetts
> (978) 742-9014, olinKILLspamembedinc.com, http://www.embedinc.com
>
> --
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>

>On Tue, Feb 26, 2002 at 10:36:00AM -0500, Olin Lathrop wrote:
> > > The grief saving answer is no. The true answer is "maybe if the
> conditions
> > > are right." Conditions being that the bit rate is slow enough and there
> > > isn't drastic changes in temperature.
> >
> > The absolute bit speed has nothing to do with it.  The relative speed error
> > is what matters.  You'd like to be within 3%, whether that's 300 baud +-9,
> > or 115.2Kbaud +- 3500.
>
>But if you slow it down then the absolute amount of time before the error
>is exceeded is lengthened.
>
>Change your examples to a time scale by inverting:
>
>300 bPS cell width: 3.3333 ms +- 0.3ms
>115k bPS cell width: 0.00886805 mS +- 0.000256 ms
>
>There's several orders of magnitude more error available at the slower speed
>before you get bit errors.

> At 01:18 PM 2/26/02 -0500, Byron A Jeff wrote:
> >On Tue, Feb 26, 2002 at 10:36:00AM -0500, Olin Lathrop wrote:
> > > > The grief saving answer is no. The true answer is "maybe if the
> > conditions
> > > > are right." Conditions being that the bit rate is slow enough and there
> > > > isn't drastic changes in temperature.
> > >
> > > The absolute bit speed has nothing to do with it.  The relative speed error
> > > is what matters.  You'd like to be within 3%, whether that's 300 baud +-9,
> > > or 115.2Kbaud +- 3500.
> >
> >But if you slow it down then the absolute amount of time before the error
> >is exceeded is lengthned.
> >
> >Change your examples to a time scale by inverting:
> >
> >300 bPS cell width: 3.3333 ms +- 0.3ms
> >115k bPS cell width: 0.00886805 mS +- 0.000256 ms
>
> Byron - please forgive me for disagreeing with you.  Olin is more correct
> than you.
>
> The baud rate is directly related to Fosc.  If Fosc changes by 1%, so does
> the baud rate.  You are correct in that one can have a slight amount more
> error at higher baud rates because of rounding error but that is a problem
> only if Fosc is not an exact multiple of the desired baud rate.

>
> Using the internal RC oscillator (4 MHz) *can* result significant rounding
> error at high baud rates - *IF* you are using standard baud rates.  For PIC
> to PIC communications, one can choose a non-standard baud rate with no
> rounding error at the desired speed.
>
> However, having said all that, I feel that using the internal RC oscillator
> for the timebase for serial comms is iffy at best.  I don't use it in my
> products - I have to operate over the temperature range of -40 through +85C
> in almost everything I ship.  The internal RC oscillator just isn't stable
> enough over that wide a temperature range.