Post by thread:[PIC]: what does bit SSPSTAT<7> do ?

>-----Original Message----- >From: spam_OUTpiclist-bouncesTakeThisOuTmit.edu [.....piclist-bouncesKILLspam@spam@mit.edu] >Sent: 01 September 2005 13:42 >To: pic microcontroller discussion list >Subject: [PIC]: what does bit SSPSTAT<7> do ? > > >hello, > >as my previous post didn't get any responses, >I rephrase my question: > >Can anyone tell me what bit SSPSTAT<7> does, >in I2C mode ? >From the mid-range reference manual: "The SMP bit is the slew rate control enabled bit. This bit is in the SSPSTAT register, and controls the slew rate of the I/O pins when in I2C mode (master or slave)." Regards Mike ======================================================================= This e-mail is intended for the person it is addressed to only. The information contained in it may be confidential and/or protected by law. If you are not the intended recipient of this message, you must not make any use of this information, or copy or show it to any person. Please contact us immediately to tell us that you have received this e-mail, and return the original to us. Any use, forwarding, printing or copying of this message is strictly prohibited. No part of this message can be considered a request for goods or services. =======================================================================

Michael Rigby-Jones wrote: {Quote hidden}> > >>-----Original Message----- >>From: piclist-bouncesKILLspammit.edu [.....piclist-bouncesKILLspam.....mit.edu] >>Sent: 01 September 2005 13:42 >>To: pic microcontroller discussion list >>Subject: [PIC]: what does bit SSPSTAT<7> do ? >> >> >>hello, >> >>as my previous post didn't get any responses, >>I rephrase my question: >> >>Can anyone tell me what bit SSPSTAT<7> does, >>in I2C mode ? >> >> > > >>From the mid-range reference manual: > >"The SMP bit is the slew rate control enabled bit. This bit is in the SSPSTAT register, and controls the slew rate of the I/O pins when in I2C mode (master or slave)." > > thanks, but how does it control the slew-rate: PIC16F877 manual states 0 = slew rate control enabled for high speed mode (400 kHz) 1 = slew rate contral disabled for standard speed mode (100 kHz and 1 MHz) what is enabling of slew rate ??? I guess they mean something like this: 0 = smitt-trigger input enabled (for any frequency you like) 1 = smitt-trigger input disabled (for any frequency you like) and above it doesn't do anything with the slew rate of the output. Is this correct ?? Stef Mientki > >

{Quote hidden}>-----Original Message----- >From: EraseMEpiclist-bouncesspam_OUTTakeThisOuTmit.edu [piclist-bouncesspam_OUTmit.edu] >Sent: 01 September 2005 15:01 >To: Microcontroller discussion list - Public. >Subject: Re: [PIC]: what does bit SSPSTAT<7> do ? > >but how does it control the slew-rate: >PIC16F877 manual states > 0 = slew rate control enabled for high speed mode (400 kHz) > 1 = slew rate contral disabled for standard speed mode (100 >kHz and 1 MHz) > >what is enabling of slew rate ??? > >I guess they mean something like this: > 0 = smitt-trigger input enabled (for any frequency you like) > 1 = smitt-trigger input disabled (for any frequency you >like) and above it doesn't do anything with the slew rate of >the output. > >Is this correct ?? > >Stef Mientki Slew rate refers to the maximum rate of change of voltage (which essential determines the rise/fall time of the clock/data signals), and the PIC can only control this on it's outputs. I don't know the specifics of exactly how it controls the slew rate, I guess some kind of compensation is applied around the pins output driver. The electrical specifications in the back of the PICs datasheet should give the relevant rise/fall times. Regards Mike ======================================================================= This e-mail is intended for the person it is addressed to only. The information contained in it may be confidential and/or protected by law. If you are not the intended recipient of this message, you must not make any use of this information, or copy or show it to any person. Please contact us immediately to tell us that you have received this e-mail, and return the original to us. Any use, forwarding, printing or copying of this message is strictly prohibited. No part of this message can be considered a request for goods or services. =======================================================================

Michael Rigby-Jones wrote: {Quote hidden}> > >>-----Original Message----- >>From: @spam@piclist-bouncesKILLspammit.edu [KILLspampiclist-bouncesKILLspammit.edu] >>Sent: 01 September 2005 15:01 >>To: Microcontroller discussion list - Public. >>Subject: Re: [PIC]: what does bit SSPSTAT<7> do ? >> >> >> > > > >>but how does it control the slew-rate: >>PIC16F877 manual states >>0 = slew rate control enabled for high speed mode (400 kHz) >>1 = slew rate contral disabled for standard speed mode (100 >>kHz and 1 MHz) >> >>what is enabling of slew rate ??? >> >>I guess they mean something like this: >> 0 = smitt-trigger input enabled (for any frequency you like) >> 1 = smitt-trigger input disabled (for any frequency you >>like) and above it doesn't do anything with the slew rate of >>the output. >> >>Is this correct ?? >> >>Stef Mientki >> >> > >Slew rate refers to the maximum rate of change of voltage (which essential determines the rise/fall time of the clock/data signals), and the PIC can only control this on it's outputs. I don't know the specifics of exactly how it controls the slew rate, I guess some kind of compensation is applied around the pins output driver. > >The electrical specifications in the back of the PICs datasheet should give the relevant rise/fall times. > > Yes, and there's is nothing depending on SSPSTAT<7>, so therefor I concluded it doesn't do anything with the slew rate. The only parameters that I could find, which are *possible* involved in SSPSTAT<7> are D034 ./ D034A and D044 / D044A D034/D044 specifies the input high/low voltage range on RC3/RC4 with smitt-trigger enabled D034A/D044A specifies the input high/low voltage range on RC3/RC4 with smitt-trigger disabled (also called SMbus) Stef > >

>Michael Rigby-Jones wrote: > >>Slew rate refers to the maximum rate of change of voltage (which >>essential determines the rise/fall time of the clock/data >signals), and >>the PIC can only control this on it's outputs. I don't know the >>specifics of exactly how it controls the slew rate, I guess some kind >>of compensation is applied around the pins output driver. >> >>The electrical specifications in the back of the PICs >datasheet should >>give the relevant rise/fall times. >> >> Stef Mientki replied: {Quote hidden}>Yes, and there's is nothing depending on SSPSTAT<7>, >so therefor I concluded it doesn't do anything with the slew rate. > >The only parameters that I could find, >which are *possible* involved in SSPSTAT<7> are >D034 ./ D034A and D044 / D044A >D034/D044 specifies the input high/low voltage range on RC3/RC4 with >smitt-trigger enabled >D034A/D044A specifies the input high/low voltage range on RC3/RC4 with >smitt-trigger disabled (also called SMbus) > What device are you refering to? There are some differences between PIC's. Using the 16F877 datasheet for example, the SMP bit controls wether or not slew rate limiting is applied in high speed (400KHz) mode. If you refer to the "I2C Bus Data Requirements" under the Electrical Characteristics section, you will see "SDA and SCL Rise time" and "SDA and SCL Fall time". For each parameter, a separate figure is given for 100KHz and 400KHz (high speed mode). If you use the MSSP in high speed mode but with slew rate limiting disabled, you would (I think) get the same rise/fall times as the 100KHz mode. The I2C/SMBus input threshold levels are controlled by the CKE bit and have nothing to do with slew rate. Regards Mike ======================================================================= This e-mail is intended for the person it is addressed to only. The information contained in it may be confidential and/or protected by law. If you are not the intended recipient of this message, you must not make any use of this information, or copy or show it to any person. Please contact us immediately to tell us that you have received this e-mail, and return the original to us. Any use, forwarding, printing or copying of this message is strictly prohibited. No part of this message can be considered a request for goods or services. =======================================================================

>What device are you refering to? There are some differences between PIC's. > >Using the 16F877 datasheet for example, the SMP bit controls wether or not slew rate limiting is applied in high speed (400KHz) mode. If you refer to the "I2C Bus Data Requirements" under the Electrical Characteristics section, you will see "SDA and SCL Rise time" and "SDA and SCL Fall time". For each parameter, a separate figure is given for 100KHz and 400KHz (high speed mode). If you use the MSSP in high speed mode but with slew rate limiting disabled, you would (I think) get the same rise/fall times as the 100KHz mode. > >The I2C/SMBus input threshold levels are controlled by the CKE bit and have nothing to do with slew rate. > > > That's the clue !! Thanks very much !! Stef > >