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PICList Thread
'[PIC] PIC SPI level conversion'
2009\09\28@213855 by Kevin

picon face

Hi,

I use a home grown proto board (5V) with a PIC16F88
w/bootloader and a Max232 chip to load programs via the pc serial port.

I would like to communicate to a TI CC1101 chip via SPI. The
TI CC1101 radio chip has voltage range of 1.8V to 3.6V. Does
anybody have a simple level conversion circuit or a favorite
chip they use to convert the 5V to 3V and vice versus ?


Thanks,
Kevin

2009\09\29@094439 by olin piclist

face picon face
Kevin wrote:
> Does
> anybody have a simple level conversion circuit or a favorite
> chip they use to convert the 5V to 3V and vice versus ?

5V to 3V only requires two resistors.

A quick and easy solution for 3V to 5V, especially for hobby projects, is to
use a 74HCT gate (or any gate with TTL inputs) at 5V power.  Its input
threshold levels are guaranteed to interpret the 3V signals correctly, and
its output will be 5V logic.


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Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\09\29@105440 by Brendan Gillatt

flavicon
face
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Kevin wrote:
{Quote hidden}

The circuit in
www.nxp.com/acrobat_download/applicationnotes/AN97055.pdf
is what I normally use to convert between two voltage levels.

Many people will tell you that you can use a voltage divider for 5v -> 3v
and rely on the 5v logic's 2.5v threshold for 3v -> 5v conversion. This
may work but it is not bidirectional and sounds a bit iffy.

- --
Brendan Gillatt | GPG Key: 0xBF6A0D94
brendan {a} brendangillatt (dot) co (dot) uk
http://www.brendangillatt.co.uk
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.7 (MingW32)

iD8DBQFKwh+uHEhZ5Ws5poERAmPfAKDGUrvFgQS+TUWUGZnX4XrTz2OCVQCcDg02
dMJlwed0LI91mZxbxgkguHI=
=hTVJ
-----END PGP SIGNATURE-----

2009\09\29@110012 by Harold Hallikainen

face
flavicon
face

{Quote hidden}

For 3.3V to 5V logic level conversion, I use some sort of 74HCT chip. The
T makes Vih low enough to accept 3.3V logic levels.

Harold

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2009\09\29@115707 by olin piclist

face picon face
Brendan Gillatt wrote:
> Many people will tell you that you can use a voltage divider for 5v ->
> 3v and rely on the 5v logic's 2.5v threshold for 3v -> 5v conversion.
> This may work but it is not bidirectional and sounds a bit iffy.

I don't see anything iffy?  All specs are met without waving of dead fish.

There is a tradeoff between speed and current consumption with the resistor
divider, but that is no different than the tradeoff of what family gate to
use for the other direction.  My standard answer is 2K ohms in series
followed by 3.9K ohms to ground for 5.0V to 3.3V, but some cases may require
lower values.  2Kohms // 3.9Kohms = 1.3Kohms, * 100pF = 130nS, so that
should be good for up to 2MHz square wave considering 100pF is very high for
on-board traces.

Do you have any fact-based objection or is your comment just silly
superstition?


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\09\29@152917 by Andy Tuthill

picon face

I have used the voltage divider option in the past to make a 5V pic talk to an Analog Devices DSP running at 3.3V.  We thought it might be iffy as well but found it worked well and avoided us needing to add another chip.  Having said that I tried to do the same with a Xilinx fpga and found it wouldn't work so it's not a perfect solution.

If you want to be certain and use a level converter start with your usual supplier (Digikey, Farnell, Newark, etc.) and see what they offer.  They can be a great place to find what's available for different functions.

Regards,
Andy

{Quote hidden}

> -

2009\09\29@155337 by Marcel Duchamp

picon face
I've been using this dual buffer for a while for 5V to 3V and vice versa:
SN74LVC2G07DCKR        
DIGIKEY: 296-13495-1-ND


It's a dual non-inverting buffer with open drain outputs.  The supply
voltage sets the input thresholds while the pull up voltage sets the
output high voltage.


{Quote hidden}

2009\09\29@165934 by Funny NYPD

picon face

>Having said that I tried to do the same with a Xilinx fpga and found it wouldn't work so it's not a perfect solution.

Any idea what makes it not working with FPGA?

Funny N.
Au Group Electronics, http://www.AuElectronics.com
http://www.AuElectronics.com/products
http://augroups.blogspot.com/




________________________________
From: Andy Tuthill <azandy63spamKILLspamhotmail.com>
To: .....piclistKILLspamspam.....mit.edu
Sent: Tuesday, September 29, 2009 3:28:54 PM
Subject: RE: [PIC] PIC SPI level conversion


I have used the voltage divider option in the past to make a 5V pic talk to an Analog Devices DSP running at 3.3V.  We thought it might be iffy as well but found it worked well and avoided us needing to add another chip.  Having said that I tried to do the same with a Xilinx fpga and found it wouldn't work so it's not a perfect solution.

If you want to be certain and use a level converter start with your usual supplier (Digikey, Farnell, Newark, etc.) and see what they offer.  They can be a great place to find what's available for different functions.

Regards,
Andy

{Quote hidden}

> -

2009\09\30@120944 by fred jones

picon face

> There is a tradeoff between speed and current consumption with the resistor
> divider, but that is no different than the tradeoff of what family gate to
> use for the other direction. My standard answer is 2K ohms in series
> followed by 3.9K ohms to ground for 5.0V to 3.3V, but some cases may require
> lower values. 2Kohms // 3.9Kohms = 1.3Kohms, * 100pF = 130nS, so that
> should be good for up to 2MHz square wave considering 100pF is very high for
> on-board traces.
>
> Do you have any fact-based objection or is your comment just silly
> superstition?


Where did you get 100pF in your calculations?  Is this just a conservative value you chose for a rough estimate?



FJ
                                           
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2009\09\30@122130 by olin piclist

face picon face
fred jones wrote:
>> There is a tradeoff between speed and current consumption with the
>> resistor divider, but that is no different than the tradeoff of what
>> family gate to use for the other direction. My standard answer is 2K
>> ohms in series followed by 3.9K ohms to ground for 5.0V to 3.3V, but
>> some cases may require lower values. 2Kohms // 3.9Kohms = 1.3Kohms, *
>> 100pF = 130nS, so that should be good for up to 2MHz square wave
>> considering 100pF is very high for on-board traces.
>>
>> Do you have any fact-based objection or is your comment just silly
>> superstition?
>
> Where did you get 100pF in your calculations?  Is this just a
> conservative value you chose for a rough estimate?

Yes, very conservative for a trace that stays on the board.


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Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\09\30@122538 by Harold Hallikainen

face
flavicon
face

{Quote hidden}

That brings up an interesting idea. How about treating the voltage divider
like a scope probe with a compensating capacitor across the top resistor.
Like with a scope, adjust the capacitor value until you get a square
waveform without overshoot. We have a resistive voltage divider in
parallel with a capacitive voltage divider.

Harold



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2009\09\30@142233 by Spehro Pefhany

picon face
At 12:37 PM 30/09/2009, you wrote:

{Quote hidden}

Sure you could.. especially if you knew the capacitance of the traces and
input(s) with some accuracy (and assuming it was reasonably stable- not much
contributed by the temperature-sensitive FR4, no fly wires etc.), but wouldn't
it be better to use a translator with solid output drive which is designed for
the job in cases where you may need high speed?

There are lots of translators with dual supplies (no sequencing
required) and many
are bidirectional (with a direction pin). This kind is cheap, fast, and pretty
much foolproof.

For example: http://focus.ti.com/lit/ds/symlink/sn74lvc2t45.pdf

Of course it's nice if you can just run everything off the same 3.3V supply and
avoid translation altogether-- there are RS232 drivers which operate from 3.3V,
so maybe that's an option for the OP.

For high-to-low, resistor dividers are okay if speed is not high and
cost is your
main concern. There is likely going to be current flowing into the input
protection network if the low voltage supply comes up later (a
potential latch-up
situation that should be checked, but it's probably okay), and
worst-case tolerances
could be on the edge of what is officially permissible depending on
the supply and
resistor tolerances, but usually it should work out well enough for
non-critical
designs. Open-drain solutions have the speed issue, but not the other concerns
since you'll pull up to the appropriate supply voltage.

BTW, keep in mind that you can't just feed 3.3V CMOS outputs into the
SDI input
of a 16F88 @5V and expect it to work reliably since they are ST- and
not TTL-level
inputs so a "high" could be as much as 80% of Vdd (4V nominally), plus you'd
like at least a few hundred mV margin beyond that, so 3.3V nominal doesn't
even come close to cutting it.

As Olin suggested, a 74HCT gate will work, as would a single-bit version of
the 2T45 translator for low-to-high. Or bit-bang the SPI and use a regular
PIC I/O port. Heck, if you are bit-banging and really trust your PIC use a
pullup to 3.3V on the output, set the pin state to low, and diddle the TRIS bit
instead-- but really I'd put a series resistor in there too. ;-)

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
@spam@speffKILLspamspaminterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2009\09\30@161308 by Sean Breheny

face picon face
Perhaps he was referring to the entire method (voltage divider for
5v->3v AND just sending 3v into the 5v logic and assuming that it will
be above the logic threshold).

Sean


On Tue, Sep 29, 2009 at 11:59 AM, Olin Lathrop
<KILLspamolin_piclistKILLspamspamembedinc.com> wrote:
{Quote hidden}

>


'[PIC] PIC SPI level conversion'
2009\10\01@163444 by Kevin
picon face

just wanted to say thanks for the suggestions.  I am going
to use the resistor divider for testing and then move to all
3.3v components when I build the six boards I need.

Regards,
Kevin

2009\10\02@095739 by Marechiare

picon face
{Quote hidden}

Kinda dirty trick - "or is your comment silly superstition?"  to
provoke an unneeded flame. That's not plain talk, that's just a dirty
trick, as for me :-(

SPI is a bus and it should be treated as a bus. With the voltage
divider you can guarantee that the output voltage won't exceed 3.3V,
but you can't guarantee it never exceed  Vdd on those 3.3V parts.

SDO, SCK, and SS from Master to Slave lines are to be driven with one
transistor each line; the transistor's drain or collector being
connected to 3.3V through a resistor and the transistor's source or
emmiter are on the ground.

Back, the slave's SDO (master's SDI) would drive the line through a
transistor, the transistor's collector being connected to 5V through a
resistor, its emmiter is on the ground.

Signals are inverted by the transistors, but you can select SCK
polarity programmatically. SDO, SDI you could invert programmatically
too if needed.

2009\10\02@104712 by olin piclist

face picon face
Marechiare wrote:
> Kinda dirty trick - "or is your comment silly superstition?"  to
> provoke an unneeded flame. That's not plain talk, that's just a dirty
> trick, as for me :-(

Your original statement just said it was bad without providing any reasoning
or supporting evidence.  That's what superstition is, belief without
reasoning or evidence.

> SPI is a bus and it should be treated as a bus.

Sometimes thinking of it as a bus is a useful abstraction, but in the end
it's still a collection of individual signals.  Either way, I don't see how
this is relevent to converting between 3.3V and 5V ends.

> With the voltage
> divider you can guarantee that the output voltage won't exceed 3.3V,
> but you can't guarantee it never exceed  Vdd on those 3.3V parts.

OK, a real argument.  Yes, for most chips you have to make sure the 5V end
doesn't try to drive the line high before the 3.3V power has come up when
using a resistor divider.  In most cases this is a minor issue because the
supplies come up at nearly the same time, so all that is needed is a little
delay in the 5V end before driving the line high.

In some mixed voltage projects I've done, the power good signal from the
last power supply in the chain is used to release all parts from reset.  In
that case no additional delay is needed since all power is up before any
microcontroller starts running.

> SDO, SCK, and SS from Master to Slave lines are to be driven with one
> transistor each line;

Well that's one way, but shouldn't be proclaimed as How It Is To Be Done
because there are certainly other ways.

{Quote hidden}

That scheme gets around the different power supplies being down at different
times.  It has its own set of issues though, so like most engineering
decisions, it's a tradeoff.  Drawbacks to this approach are that the signals
are inverted as you said, a fair amount of added discrete parts, and the
speed of the rising edges versus current consumption tradeoff is worse than
for a resistor divider.  Nothing is free.  This scheme might be worth it
when the 5V and 3.3V power supplies could go up and down independently.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\02@121907 by Marechiare

picon face
>> Kinda dirty trick - "or is your comment silly superstition?"  to
>> provoke an unneeded flame. That's not plain talk, that's just a dirty
>> trick, as for me :-(
>
> Your original statement just said it was bad without providing any reasoning
> or supporting evidence.  That's what superstition is, belief without
> reasoning or evidence.

I am not sure I understand what you mean under "Your original statement".
You used word "silly". Some may see it to be rather offensive
regardless of the fact any reasoning or supporting evidence had been
provided.


> a fair amount of added discrete parts,

One FET from a pack and a resistor instead of two resistors for the
divider - this even could save some space on a PCB and count the
number of discrete parts down.


> and the speed of the rising edges versus current consumption
> tradeoff is worse than for a resistor divider.

Energy consumption, not current consumption may be important.  With
3.3V you can afford more current than with 5V for the same energy
spent. And you can afford even more current to inputs since when
charging inputs a lot of current is getting wasted through the bottom
resistor of the divider. So, for the same energy consumption the speed
of the rising edges may not necessarily be lower.

2009\10\02@133007 by Spehro Pefhany

picon face
At 12:18 PM 02/10/2009, you wrote:

>Energy consumption, not current consumption may be important.  With
>3.3V you can afford more current than with 5V for the same energy
>spent. And you can afford even more current to inputs since when
>charging inputs a lot of current is getting wasted through the bottom
>resistor of the divider. So, for the same energy consumption the speed
>of the rising edges may not necessarily be lower.

The open drain/pullup method gives asymmetrical rise/fall time. Fall
time is relatively low (Rds(on) * C) and rise time is  proportional to
R*C. The divider method gives (very close to) equally slowed rise and fall
times assuming a CMOS output and reasonable resistor values. Ignoring that..

For a 1:2 ratio of divider resistances (divider ratio 2/3) and
5V/3.3V supplies, and equal RC product, we get a current ratio of about
3:1 in favor of the divider, and a power consumption ratio of about 2:1,
also in favor of the divider.

You don't see a break-even in terms of power until you reach a 2:1
ratio in supply voltages (eg. translating from 5.0V to 2.5V).

Of course neither approaches the low power consumption of some translator
chips-- in the uA range under static conditions.

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
RemoveMEspeffTakeThisOuTspaminterlog.com             Info for manufacturers: http://www.trexon.com
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2009\10\02@135728 by Michael Rigby-Jones

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face
TI have a nice table showing voltage translator products here:

http://focus.ti.com/download/aap/pdf/VLT_PF_Overview.pdf

Regards

Mike

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2009\10\02@145032 by Marechiare

picon face

> For a 1:2 ratio of divider resistances (divider ratio
> 2/3) and 5V/3.3V supplies, and equal RC product,
> we get a current ratio of about 3:1 in favor of the
> divider, and a power consumption ratio of about 2:1,
> also in favor of the divider.
>
> You don't see a break-even in terms of power until
> you reach a 2:1 ratio in supply voltages (eg. translating
> from 5.0V to 2.5V).

I may disagree with Olin from time to time, because I almost always
understand his logic. He possesses a rare talent to express his
thoughts clearly and concisely (my all time reference level of the
talent:  AISBERG E. - Le transistor? Mais c'est trиs simple!)

But forgive me, I don't understand your writing and thus can't discuss it.

2009\10\02@191727 by Spehro Pefhany

picon face


>  But forgive me, I don't understand your writing and thus can't discuss it.

It's just a fun mathematical exercise-- algebra, Ohm's law and Thevenin
equivalents, and time constants.

Hopefully this will help--

http://speff.com/divider_pullup.jpg

I left out some steps in deriving the design equations and more steps at
the end to keep this to one page, but it's just algebra.

My conclusion is that the voltage divider has lower maximum power
consumption unless Va >= 2*Vb.

So, it's better for 5V->3.3V, equal for 5V->2.5V and worse for 5V->1.8V,
all other things being equal.

Similarly, it's easy to see that the max current drawn is always better
with the voltage divider (they are only equal when Vb == 0).

One uses power when low and the other when high, so the comparisons are
a bit flawed in real situations such as SPI!

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
spamBeGonespeffspamBeGonespaminterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2009\10\03@122534 by Marechiare

picon face
> I left out some steps in deriving the design equations and
> more steps at the end to keep this to one page, but it's
> just algebra.
>
> My conclusion is that the voltage divider has lower maximum
> power consumption unless Va >= 2*Vb.
>
> So, it's better for 5V->3.3V, equal for 5V->2.5V and worse
> for 5V->1.8V, all other things being equal.
>
> Similarly, it's easy to see that the max current drawn is
> always better with the voltage divider (they are only equal
> when Vb == 0).

Yeah, Algebra is The Argument. Let's check your math with just common
sense and some simple arithmetics (to SW: Ohms Law involved).

Voltages are 5V and 3V, those OP requested.

For Voltage Divider:
Voltage divider is 2K + 3K.
Power consumption factor 5V * 5V / 5KOhm = 5mW

For FET & Resistor
Power consumption factor 5mW, thus resistor is 3V * 3V / 5mW = 1.8 KOhm

That is, 2K + 3K Voltage Divider would consume the same power as FET +
1.8K resistor

Let's compare their timings now:

Yes, 5V / 2K = 0.0025 slope factor is better than 3V / 1.8K = 0.0017

But, please, keep in mind that the above is true only for rising edge.
For falling edge the divider works through the same 2K and the FET
works directly through its aprox 1 Ohm Rds(On).

Thus the sum of rising and falling transition times is considerably
worse for the "Voltage Divider" case compared to the case of FET +
resistor when both approaches are consuming the same power.

Moreover this asymmetrical rise/fall time DOES work for "FET +
resistor" approach.  It's much better to synch to sharp falling edge
as in the "FET + resistor" approach, than to fuzzy many factors
dependent any edge as in "Voltage Divider" case. If I am not mistaken
the phase of SCK could be programmatically adjusted for newer PICs.
Set the edge sharp, and adjust the SCK phase properly.

2009\10\03@124413 by olin piclist

face picon face
Marechiare wrote:
> For Voltage Divider:
> Voltage divider is 2K + 3K.
> Power consumption factor 5V * 5V / 5KOhm = 5mW
>
> For FET & Resistor
> Power consumption factor 5mW, thus resistor is 3V * 3V / 5mW = 1.8
> KOhm

Exactly.  But to get the same speed, meaning same signal impedence, you
would need 1.2Kohms since 2Kohm // 3Kohm = 1.2Kohm.

> It's much better to synch to sharp falling edge
> as in the "FET + resistor" approach, than to fuzzy many factors
> dependent any edge as in "Voltage Divider" case.

Once again, there is no inherently better approach, so please stop making it
sound like yours is.  That is bad engineering.  What is better depends on
various factors of the design at hand.  In different situations the various
characteristics of any one approach will have different costs or advantages,
which change which approach will be better per situation.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\03@153630 by Marechiare

picon face
>> For Voltage Divider:
>> Voltage divider is 2K + 3K.
>> Power consumption factor 5V * 5V / 5KOhm = 5mW
>>
>> For FET & Resistor
>> Power consumption factor 5mW, thus resistor is 3V * 3V / 5mW = 1.8
>> KOhm
>
> Exactly.  But to get the same speed, meaning same signal impedence, you
> would need 1.2Kohms since 2Kohm // 3Kohm = 1.2Kohm.

On falling edge impedance of FET - Rds(On) - is much less than 1.2K.
On rising edge I don't see how does mentioned in your calcs 3Kohm
divider's bottom resistor help to speed the rising.


>> It's much better to synch to sharp falling edge
>> as in the "FET + resistor" approach, than to fuzzy
>> many factors dependent any edge as in "Voltage
>>Divider" case.
>
> Once again, there is no inherently better approach,
> so please stop making it sound like yours is.

Do you really want ME to adjust the sound? This kind of perception
depends on a listener, not on a speaker.


> ... What is better depends on various factors of the
> design at hand.  In different situations the various
> characteristics of any one approach will have different
> costs or advantages, which change which approach
> will be better per situation.

That's true.

2009\10\03@160928 by olin piclist

face picon face
Marechiare wrote:
>> Exactly. But to get the same speed, meaning same signal impedence,
>> you would need 1.2Kohms since 2Kohm // 3Kohm = 1.2Kohm.
>
> On rising edge I don't see how does mentioned in your calcs 3Kohm
> divider's bottom resistor help to speed the rising.

This is very basic electronics.  Look up something called "Thevenin
Equivalent".

>> Once again, there is no inherently better approach,
>> so please stop making it sound like yours is.
>
> Do you really want ME to adjust the sound? This kind of perception
> depends on a listener, not on a speaker.

I want you and everyone else to stick to good engineering practises.
Absolute statements about one approach always being better than another when
there are clearly tradeoffs envolved is superstition, not engineering.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\03@173301 by Wouter van Ooijen

face picon face
>>> It's much better to synch to sharp falling edge

That was you stating that something is better (without qualification)

>> Once again, there is no inherently better approach,
>> so please stop making it sound like yours is.

Olin denies that that something is always better, and says you should
not say so.

> Do you really want ME to adjust the sound?

Yes, I think he does, because he is right.

>> ... What is better depends on various factors of the
>> design at hand.

> That's true.

And you admit he's right. So why are you surprised he tells you to be
less absolute?

That was just text analysis. Technically, there are at least 4 SPI
variants, including sampling on the rising edge and sampling on the
falling edge. A nice sharp falling edge might be good if it is the
sampling edge, or might be useless when it is not (might, because some
internal action might still occur on the non-active edge). So indeed
"there is no inherently better approach", there are just approaches that
are less bad in a particular situation.

--

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu

2009\10\04@142322 by Marechiare

picon face
>>> Exactly. But to get the same speed, meaning same signal
>>> impedence, you would need 1.2Kohms since
>>> 2Kohm // 3Kohm = 1.2Kohm.
>>
>> On rising edge I don't see how does mentioned in your calcs
>> 3Kohm divider's bottom resistor help to speed the rising.
>
> This is very basic electronics.  Look up something called
> "Thevenin Equivalent".

Interesting, obviously, removing the bottom resistor from the divider
would increase the speed of rising (assuming inputs would tolerate
it). But, according to your logic/formula removing the bottom resistor
would increase impedance and, thus, decrease the speed of rising.


>>> Once again, there is no inherently better approach,
>>> so please stop making it sound like yours is.
>>
>> Do you really want ME to adjust the sound? This kind of perception
>> depends on a listener, not on a speaker.
>
> I want you and everyone else to stick to good engineering practises.
> Absolute statements about one approach always being better than another when
> there are clearly tradeoffs envolved is superstition, not engineering.

Aha, I see, the problem is that I ommited the magic word "COULD". Ok,
if I had written " It COULD be much better to synch to sharp falling
edge" - would the rest hold true about FET + resistor to VERY PROBABLY
be better than the divider in many designs?

2009\10\04@151010 by Bob Blick

face
flavicon
face
Marechiare wrote:
>>>> Exactly. But to get the same speed, meaning same signal
>>>> impedence, you would need 1.2Kohms since
>>>> 2Kohm // 3Kohm = 1.2Kohm.
>>> On rising edge I don't see how does mentioned in your calcs
>>> 3Kohm divider's bottom resistor help to speed the rising.
>> This is very basic electronics.  Look up something called
>> "Thevenin Equivalent".
>
> Interesting, obviously, removing the bottom resistor from the divider
> would increase the speed of rising (assuming inputs would tolerate
> it). But, according to your logic/formula removing the bottom resistor
> would increase impedance and, thus, decrease the speed of rising.

Not exactly. With two resistors the impedance is 1.2k and with only one
it's 2k. But the equivalent voltages are 3.3 and 5 respectively. If you
are driving logic with TTL(1.2 volt) thresholds the rise times will be
very close.

Cheerful regards,

Bob

2009\10\04@153427 by Wouter van Ooijen

face picon face
> Aha, I see, the problem is that I ommited the magic word "COULD". Ok,
> if I had written " It COULD be much better to synch to sharp falling
> edge" - would the rest hold true about FET + resistor to VERY PROBABLY
> be better than the divider in many designs?

That would very probably not be true, but it depends on your value of
many. 1k out of 1M is still quite a lot, so it might qualify for your
'many'.

Think for instance about
- inverting the signal
- slower rising edge
- slightly more expensive components (including a FET which probably has
a higher risk of failure, especially in a high-radiation environment)
- takes current from the lower voltage supply instead of taking it from
the higher voltage supply (probably just as likely to be an advantage
too, but still an argument against blanket-like statements)

--

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: http://www.voti.nl/hvu

2009\10\04@160234 by olin piclist

face picon face
Marechiare wrote:
>>> On rising edge I don't see how does mentioned in your calcs
>>> 3Kohm divider's bottom resistor help to speed the rising.
>>
>> This is very basic electronics. Look up something called
>> "Thevenin Equivalent".
>
> Interesting, obviously, removing the bottom resistor from the divider
> would increase the speed of rising

No, it wouldn't.  The bottom resistor contributes to lowering the output
impedence of the voltage divider.  Lower output impedence causes faster
output edges.

> But, according to your logic/formula removing the bottom resistor
> would increase impedance and, thus, decrease the speed of rising.

Yes, but it's not just my logic, it's basic electronics.  You apparently
didn't look up "Thevenin Equivalent" like I suggested.  You really need to
do that before commenting on this circuit again.  In fact, anyone fuzzy on
Thevenin and Norton equivalents should refrain from pontificating on
electronics to avoid embarassement and confusing newbies.

> Aha, I see, the problem is that I ommited the magic word "COULD". Ok,
> if I had written " It COULD be much better to synch to sharp falling
> edge" - would the rest hold true about FET + resistor to VERY PROBABLY
> be better than the divider in many designs?

The I disagree about the "very probably".  It sounds like there is still
only One Right Way in your mind.  While a grounded source N FET could be the
right tradeoff in some cases, it also has significant enough issues that
making it sound like it's almost always the right answer is misleading.  As
we've already discussed, there are several ways to go from 5V to 3.3V logic.

A resistor divider is cheap and simple.  Drawbacks are that it has
relatively high (compared to a CMOS logic gate) output impedence or requires
high current, and that it draws current continuously at logic high.

A grounded common emitter/source transistor is faster on output falling
edges.  Drawbacks are that is costs a little more, rising edges are slower
for the same current (at 5V to 3.3V), and that it inverts.

A level shifting gate is probably the best way from a purely electrical
standpoint, but costs even more, requires more connections, and probably
more board space.

The point is there is no One Right Answer.  The right answer for a
particular design depends on the relative weighting of all the advantages
and disadvantages of each method.  For example, in one project I needed to
connect the UART output of a dsPIC running at 5V to the UART input of a 18F
running at 3.3V, the baud rate was 115.2K, and both processors were on the
same board with a common ground.  In that case a resistor divider was the
clear choice since it was cheap, small, plenty fast enough for 8uS/bit, and
the dsPIC wouldn't be released from reset until both supplies were up and
stable.  A inverting solution, like your FET or transistor method, would
have made no sense.  A level shifter chip would have worked, but would have
cost more and taken more board space, especially since I only needed to
convert that one line.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@160346 by Marechiare

picon face
>>>>> Exactly. But to get the same speed, meaning same signal
>>>>> impedence, you would need 1.2Kohms since
>>>>> 2Kohm // 3Kohm = 1.2Kohm.
>>>> On rising edge I don't see how does mentioned in your calcs
>>>> 3Kohm divider's bottom resistor help to speed the rising.
>>> This is very basic electronics.  Look up something called
>>> "Thevenin Equivalent".
>>
>> Interesting, obviously, removing the bottom resistor from the divider
>> would increase the speed of rising (assuming inputs would tolerate
>> it). But, according to your logic/formula removing the bottom resistor
>> would increase impedance and, thus, decrease the speed of rising.
>
> Not exactly. With two resistors the impedance is 1.2k and with only one
> it's 2k. But the equivalent voltages are 3.3 and 5 respectively. If you
> are driving logic with TTL(1.2 volt) thresholds the rise times will be
> very close.

TI CC1101 is not TTL.
>From its datasheet:
4.8 DC Characteristics
Logic "1" input voltage (VDD-0.7V) to VDD

For your 3.3V it will be >=2.6V.
Obviously the presence of the bottom resistor of the divider would
slow the signal rising to that level, the times with/without the
resistor should not be "very close".

2009\10\04@162539 by Bob Blick

face
flavicon
face
Marechiare wrote:
{Quote hidden}

Using the word "obviously" doesn't make it so. Show me the math.

If you can't drive your chip's input with 5 volts, you either use a
divider or some form of logic conversion from the 3.3V supply.

A divider from 5V logic using 2k/3K resistors is very close to a 1.2K
resistor from 3.3V logic. Using a FET or other active device for
pulldown and a resistor for pullup will speed the fall time, but the
rise time will be the same.

I'm not trying to be cranky or fight about any of this, I just want to
make sure you are clear on the electrical models we're discussing. Olin
is on very solid ground.

Cheerful regards,

Bob

2009\10\04@163830 by Marechiare

picon face
>> Aha, I see, the problem is that I ommited the magic word "COULD". Ok,
>> if I had written " It COULD be much better to synch to sharp falling
>> edge" - would the rest hold true about FET + resistor to VERY PROBABLY
>> be better than the divider in many designs?
>
> That would very probably not be true, but it depends on your value of
> many. 1k out of 1M is still quite a lot, so it might qualify for your
> 'many'.
>

Ok if I removed VERY from my statement, would I qualify to avoid the
kind of crucifixion for propagating bad EE practicies?

> Think for instance about
> - inverting the signal

So, you think only 1k out of 1M designs do not care of it? Others
can't invert the bits programmatically (if needed).

> - slower rising edge
Rising edge for the voltage divider is faster sort of 30%, but falling
edge is slower much much more.
So, you think that for 999K of 1M designs these 30% are vital for the
rising. And much faster falling does not matter?

> - takes current from the lower voltage supply
> instead of taking it from the higher voltage supply
> (probably just as likely to be an advantage too, but
> still an argument against blanket-like statements)

The main advantage is that it references to the input's chip Vdd. The
gap for logic "1" input voltage is quite narrow. With the divider you
are risking to either overvoltage input or just not reach the logic
"1".

etc, etc

2009\10\04@172055 by Marechiare

picon face
>> For your 3.3V it will be >=2.6V.
>> Obviously the presence of the bottom resistor of the
>> divider would slow the signal rising to that level, the
>> times with/without the resistor should not be "very close".
>>
>
> Using the word "obviously" doesn't make it so. Show me the math.

Well, perhaps I'm missing something, let's look:

Olin wrote:
> My standard answer is 2K ohms in series
> followed by 3.9K ohms to ground for 5.0V to 3.3V

Do I understand it correctly:
- The output connects to 2K resistor;
- The other leg of that 2K resistor is connected to 3.9K resistor;
- The other leg of that 3.9K resistor is connected to ground;
- The input is connected in between 2K and 3.9K resistors;

If so, do you realize that the signal on the input would approximate
5V * 3.9 / (2 + 3.9) = 3.305 V forever?
In fact, due to the output is not exactly 5V, it's sort of 4.7V, the
signal on the input capacitance would approximate 3.1V forever.

The threshold voltage 2.6V is quite close to that 3.1V and the
approximation curve is quite smooth, so the input signal would reach
2.6V later than it would reach when there is no that 3.9K resistor. In
the latter case it would approximate to 4.7 V and would pass 2.6V at a
good speed thus much earlier.

You don't need math to get it. What you need is just very basic
understanding how voltage on a capacitance is changing when the
capacitance is connected to DC source through a resistor.

Kinda can't get rid of a stupid feeling that I participated in a
similar discussion in my previous reincarnation many years ago.

2009\10\04@172402 by Spehro Pefhany

picon face
At 04:03 PM 10/4/2009, you wrote:
{Quote hidden}

Well, if you connect the same upper resistor to 300 DC it will have an even
faster rise to 0.7* 3.3 VDC, but it's precisely as pointless a comparison
as your example since it violates the abs. max. ratings of the chip and
thus is not a valid solution.

Do you know the simple equation that the v(t) follows?

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
TakeThisOuTspeffEraseMEspamspam_OUTinterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2009\10\04@174651 by Marechiare

picon face
{Quote hidden}

In this thread generalization is prohibited by some. It would be
better to say "may be pointless to some under some special
circumstances".


> since it violates the abs. max. ratings of the chip and
> thus is not a valid solution.

I said: > (assuming inputs would tolerate it).


> Do you know the simple equation that the v(t) follows?

You may wish to ask Olin. His favourite job interview question to ask,
if I am not mistaken, is about the equation of a voltage on a
capacitance connected to a DC source through a resistor.

2009\10\04@175515 by Bob Blick

face
flavicon
face
Marechiare wrote:

>> since it violates the abs. max. ratings of the chip and
>> thus is not a valid solution.
>
> I said: > (assuming inputs would tolerate it).

Fine, if you wish to change the rules in the middle of the game, you
win, have fun! I don't so much care for "Calvinball".

Cheerful regards,

Bob

2009\10\04@180552 by olin piclist

face picon face
Marechiare wrote:
> The main advantage is that it references to the input's chip Vdd. The
> gap for logic "1" input voltage is quite narrow. With the divider you
> are risking to either overvoltage input or just not reach the logic
> "1".

Not really in a typical case.  Let's say we have a nominal 5V +-2% (just
about any LDO can do that) input and are using 5% resistors, 2Kohms followed
by 3.9Kohms to ground.  The worst case high output is 5.1V into a
1900ohm,4095ohm divider, which comes out to 3.48V.  The worst case low is
4.9V into 2100ohm,3705ohm divider, which comes out to 3.13V.

Let's again say we're using a 2% LDO on the 3.3V side, so it can range from
3.37V to 3.23V.  About the highest logic high threshold you'll encounter is
80% of the supply, which is what PIC inputs with Schmitt triggers have.  The
worst case logic high threshold is therefore 3.73V * 0.8 = 2.69V.  That's
still significantly less than the lowest high of 3.13V computed above.

On the other end, the highest high of 3.48V is only 250mV above the lowest
possible Vdd.  There won't be any meaningful current thru any protection
diode at 250mV.

If you really care you can use 1% resistor, which nowadays cost the same as
5% anway.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@181408 by olin piclist

face picon face
Marechiare wrote:
>> My standard answer is 2K ohms in series
>> followed by 3.9K ohms to ground for 5.0V to 3.3V
>
> Do I understand it correctly:
> - The output connects to 2K resistor;
> - The other leg of that 2K resistor is connected to 3.9K resistor;
> - The other leg of that 3.9K resistor is connected to ground;
> - The input is connected in between 2K and 3.9K resistors;

Yes.

> The threshold voltage 2.6V is quite close to that 3.1V and the
> approximation curve is quite smooth, so the input signal would reach
> 2.6V later than it would reach when there is no that 3.9K resistor.

I can make a much faster circuit too if it doesn't have to work right.  Your
hypothetical circuit is pointless since it's violating the maximum output
voltage spec.

Think of it this way:  Compare two circuits, one is a perfect 0 to 5V square
wave followed by the 2K,3.9K ohm divider.  The other is a perfect 3.3V
square wave followed just by 2K ohms in series.  Now assume each is driving
the same capacitive load.  Which one will have faster rise and fall times?

For extra credit show the Thevenin equivalent of each circuit.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@182207 by Marechiare

picon face
>>> since it violates the abs. max. ratings of the
>>> chip and thus is not a valid solution.
>>
>> I said: > (assuming inputs would tolerate it).
>
> Fine, if you wish to change the rules in the middle
> of the game, you win, have fun! I don't so much
> care for "Calvinball".

If you stopped understanding something, this doesn't necessarily mean
that rules have changed. This sub-discussion about "bottom devider's
resistor" was initiated by Olin:

***
>> For FET & Resistor
>> Power consumption factor 5mW, thus resistor is
>> 3V * 3V / 5mW = 1.8 KOhm
>
> Exactly.  But to get the same speed, meaning same signal
> impedence, you would need 1.2Kohms since
> 2Kohm // 3Kohm = 1.2Kohm.
***
He propopsed an idea that an impedance calculated as (R1*R)/(R1+R2)
would reflect the "speed" of the signal - the lower impedance - the
higher speed. I objected it with the example to remove the bottom
resistor, - the impedance will be higher, and the speed will be
higher. That's it, nothing more, no rules changed. Your "Calvinball"
sarcasm, as for me, is not applicable here.

2009\10\04@182317 by olin piclist

face picon face
Marechiare wrote:
>> Do you know the simple equation that the v(t) follows?
>
> You may wish to ask Olin.

That would be pointless since the purpose was to see if *you* know the
answer.

> His favourite job interview question to ask,
> if I am not mistaken, is about the equation of a voltage on a
> capacitance connected to a DC source through a resistor.

No, that's too easy.  Even a digital guy can get that.  My first question is
a very simple circuit with one ideal opamp and two resistors, and I ask for
a sketch of output voltage as a function of input voltage.  It's amazing how
many people don't get it or struggle with it.  The ones that use rules of
thumb for how opamps work never get it because this circuit deliberately
doesn't fall into the catagory where the "usual" rule of thumb works.  I
don't want the kind of engineer that relies on rules instead of
understanding.

Once someone gets past this moron-level question, then I throw a few more at
them until I have a good feel for what the candidate can and can't do.  It's
actually the thought processes I'm interested in watching more than hearing
the answer.


********************************************************************
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(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@183153 by olin piclist

face picon face
Marechiare wrote:
> He propopsed an idea that an impedance calculated as (R1*R)/(R1+R2)
> would reflect the "speed" of the signal - the lower impedance - the
> higher speed.

Yes.

> I objected it with the example to remove the bottom
> resistor, - the impedance will be higher, and the speed will be
> higher. That's it, nothing more, no rules changed.

Yes they have.  The output will now go to 5V instead of 3.3V, which is a
violation of the rule that the output must drive a 3.3V input within its
spec.

You clearly still haven't looked up Thevenin Equivalent.  Go do that.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@183315 by Marechiare

picon face
{Quote hidden}

Well, if you don't want talking about "hypothetical circuit", let us
not. Let's compare the OP asked about:

I did that in one of my previous posts:

***
{Quote hidden}

***

Do I need to repeat that

> the sum of rising and falling transition times is considerably
> worse for the "Voltage Divider" case compared to the case of FET +
> resistor when both approaches are consuming the same power.

2009\10\04@185038 by Marechiare

picon face
>> He propopsed an idea that an impedance calculated as
> (R1*R2)/(R1+R2) would reflect the "speed" of the signal -
> the lower impedance - the higher speed.
>
> Yes.
>
>> I objected it with the example to remove the bottom
>> resistor, - the impedance will be higher, and the speed
>> will be higher. That's it, nothing more, no rules changed.
>
> Yes they have.  The output will now go to 5V instead of 3.3V,
> which is a violation of the rule that the output must drive
> a 3.3V input within its spec.

Well, the idea is scalable as one might expect. Decrease divider's
bottom resistor R2 by 0.1% (to stay within specs). You'll get lower
impedance according to your (R1*R2)/(R1+R2).
Is not it obvious that despite the fact that impedance gets lower, the
speed of rising will be lower, not greater as you stated above?

2009\10\04@190213 by Spehro Pefhany

picon face
At 06:50 PM 10/4/2009, you wrote:
> >> He propopsed an idea that an impedance calculated as
> > (R1*R2)/(R1+R2) would reflect the "speed" of the signal -
> > the lower impedance - the higher speed.
> >
> > Yes.
> >
> >> I objected it with the example to remove the bottom
> >> resistor, - the impedance will be higher, and the speed
> >> will be higher. That's it, nothing more, no rules changed.
> >
> > Yes they have.  The output will now go to 5V instead of 3.3V,
> > which is a violation of the rule that the output must drive
> > a 3.3V input within its spec.
>
>Well, the idea is scalable as one might expect. Decrease divider's
>bottom resistor R2 by 0.1% (to stay within specs). You'll get lower
>impedance according to your (R1*R2)/(R1+R2).
>Is not it obvious that despite the fact that impedance gets lower, the
>speed of rising will be lower, not greater as you stated above?

Does the number 1-1/e mean anything to you?

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
RemoveMEspeffspamTakeThisOuTinterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2009\10\04@190346 by olin piclist

face picon face
Marechiare wrote:
> Is not it obvious that despite the fact that impedance gets lower, the
> speed of rising will be lower, not greater as you stated above?

This is getting silly.  Report back when you've looked up Thevenin
Equivalent.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\04@190839 by Marechiare

picon face
{Quote hidden}

Why are you asking that?

2009\10\04@193403 by Marechiare

picon face
{Quote hidden}

So, may I conclude that you insist that for your circuit

"perfect 0 to 5V square wave followed by the 2K,3.9K ohm
divider, driving some capacitive load connected to ground"

when we decrease divider's bottom resistor 3.9K to 3.85K, the time to
rise the signal on the capacitor from 0V to 4.9V will decrease as per
your statement that - the lower impedance - the higher speed of signal
rising on that capacitor.

2009\10\04@194440 by Marechiare

picon face
> when we decrease divider's bottom resistor 3.9K to 3.85K,
> the time to rise the signal on the capacitor from 0V to 4.9V
> will decrease as per your statement that - the lower impedance -
> the higher speed of signal rising on that capacitor.

Siorry, a typo, should be "from 0V to 2.9V" not "from 0V to 4.9V"

Thus

So, may I conclude that you insist that for your circuit

"perfect 0 to 5V square wave followed by the 2K,3.9K ohm
divider, driving some capacitive load connected to ground"

when we decrease divider's bottom resistor 3.9K to 3.85K, the time to
rise the signal on the capacitor from 0V to 2.9V will decrease as per
your statement that - the lower impedance - the higher speed of signal
rising on that capacitor.

2009\10\04@194442 by Spehro Pefhany

picon face
At 07:08 PM 10/4/2009, you wrote:
{Quote hidden}

To evaluate your background knowledge.

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speffEraseMEspam.....interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2009\10\04@195807 by Marechiare

picon face
>> >>Well, the idea is scalable as one might expect. Decrease
>> >>divider's bottom resistor R2 by 0.1% (to stay within specs).
>> >>You'll get lower impedance according to your (R1*R2)/(R1+R2).
>> >>Is not it obvious that despite the fact that impedance gets
>> >>lower, the speed of rising will be lower, not greater as you
>> >>stated above?
>> >
>> > Does the number 1-1/e mean anything to you?
>>
>>Why are you asking that?
>
> To evaluate your background knowledge.

To evaluate your school knowledge of physics:

For the circuit:

"perfect 0 to 5V square wave followed by the 2K,3.9K ohm
divider, driving some capacitive load connected to ground"

We decrease divider's bottom resistor 3.9K to 3.85K. The impedance as
per Olin (R1*R2)/(R1+R2) will decrease.

How will change the time to rise the signal on the capacitor from 0V to 2.9V ?

Will it decrease as per Olin's statement that - the lower impedance -
the higher speed of signal
rising on that capacitor.

2009\10\04@200551 by Marechiare

picon face
Guys, I need to take a break for about 20 hours, sorry.

See you later.

On Mon, Oct 5, 2009 at 2:58 AM, Marechiare <EraseMEmarechiarespamgmail.com> wrote:
{Quote hidden}

2009\10\05@003313 by Mark Rages

face picon face
On Sun, Oct 4, 2009 at 6:05 PM, Marechiare <RemoveMEmarechiareEraseMEspamEraseMEgmail.com> wrote:
> Guys, I need to take a break for about 20 hours, sorry.
>
> See you later.
>

When you get back,
http://en.wikipedia.org/wiki/Th%C3%A9venin%27s_theorem

--
Mark Rages, Engineer
Midwest Telecine LLC
RemoveMEmarkragesspam_OUTspamKILLspammidwesttelecine.com

2009\10\05@073953 by olin piclist

face picon face
Marechiare wrote:
> So, may I conclude that you insist that for your circuit
>
> "perfect 0 to 5V square wave followed by the 2K,3.9K ohm
> divider, driving some capacitive load connected to ground"
>
> when we decrease divider's bottom resistor 3.9K to 3.85K, the time to
> rise the signal on the capacitor from 0V to 2.9V will decrease as per
> your statement that - the lower impedance - the higher speed of signal
> rising on that capacitor.

No, that is not what I said.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\05@091932 by Marechiare

picon face
Mark Rages wrote:
>
> When you get back,
> http://en.wikipedia.org/wiki/Th%C3%A9venin%27s_theorem

And what is your answer to the next:

***
For the circuit:

"perfect 0 to 5V square wave followed by the 2K,3.9K ohm divider,
driving some capacitive load" (the capacitive load being connected
between the middle of the divider and ground).

We decrease divider's bottom resistor 3.9K to 3.85K, the top divider's
resistor 2K remains the same. The impedance as per Olin
(R1*R2)/(R1+R2) will decrease.

How will change the time to rise the signal on the capacitor from 0V to 2.9V ?

Will it decrease as per Olin's statement that - the lower impedance -
the higher speed of signal rising on that capacitor.
***

Just "Yes, the time will decrease" or "No, the time will increase".
This should not be a problem to you if you are sure you are
referencing me to a relevant web link.

Thanks.

2009\10\05@093458 by olin piclist

face picon face
Marechiare wrote:
> How will change the time to rise the signal on the capacitor from 0V
> to 2.9V ?

This is the wrong question, which is probably why you are disagreeing with
everyone else.  The right question is "How will the rise time from 0V to 80%
(or any fixed percentage) of the final value change?".


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2009\10\05@113657 by Mark Rages

face picon face
On Mon, Oct 5, 2009 at 7:19 AM, Marechiare <RemoveMEmarechiareTakeThisOuTspamspamgmail.com> wrote:
{Quote hidden}

You are changing the voltage the circuit is dividing to.

Rise time is always defined relative to "full" voltage, not some
absolute 2.9V.  So relative to the new full voltage of 3.29V, the time
will decrease.

Anyway, the subject is 5V to 3.3V conversion.  Suggesting conversion
to other levels is not very interesting.

Regards,
Mark
markrages@gmail
--
Mark Rages, Engineer
Midwest Telecine LLC
EraseMEmarkragesspamspamspamBeGonemidwesttelecine.com

2009\10\05@145743 by Marechiare

picon face
Mark Rages wrote:
> Anyway, the subject is 5V to 3.3V conversion.  Suggesting
> conversion to other levels is not very interesting.

No, subject is 5V to 3.0V conversion acoording to OP: "Does
anybody have a simple level conversion circuit or a favorite
chip they use to convert the 5V to 3V and vice versus ?"

Mark Rages wrote:
> Rise time is always defined relative to "full" voltage, not
> some absolute 2.9V.  So relative to the new full voltage
> of 3.29V, the time will decrease.

So you insist that "3.29V to 3.3V" is conceptually different to "2.9V
to 3.0V"? Hmm. Well, let it be 2.99V


Olin Lathrop wrote:
> Marechiare wrote:
>> How will change the time to rise the signal on the capacitor
>> from 0V to 2.9V ?
>
> This is the wrong question, which is probably why you are
> disagreeing with everyone else.

I am not sure I understand the concept "wrong question". Wrong could
be an answer, not question, as for me.

> The right question is "How will the rise time from 0V to 80%
> (or any fixed percentage) of the final value change?".

Aha, 3V * 80% = 2.4V not 2.9V. So you insist that "2.4V to 3.0V" is
conceptually different to "2.9V to 3.0V"? Hmm. Well, let it be 2.4V.


I wrote earlier:
> He propopsed an idea that an impedance calculated as (R1*R)/(R1+R2)
> would reflect the "speed" of the signal - the lower impedance - the
> higher speed.

Olin replied:
>Yes.


So the "right" questions are:

For Olin:

***
For the circuit:

"perfect 0 to 5V square wave followed by the 2K,3.0K ohm divider,

driving some capacitive load" (the capacitive load being connected
between the middle of the divider and ground).

We decrease divider's bottom resistor 3.0K to 2.95K, the top divider's
resistor 2K remains the same. The impedance as per Olin

(R1*R2)/(R1+R2) will decrease.

How will be the time to rise the signal on the capacitor from 0V to
80% of 3.0V (that is 2.4V) in the case of 2.95K bottom resistor
compared to the rise time when the bottom resistor is 3.0K?

Will it decrease as per Olin's proposition  - the lower impedance -
the higher speed of signal?
***



For Mark Rages:

***
For the circuit:

"perfect 0 to 5V square wave followed by the 2K,3.0K ohm divider,

driving some capacitive load" (the capacitive load being connected
between the middle of the divider and ground).

We decrease divider's bottom resistor 3.0K to 2.95K, the top divider's
resistor 2K remains the same. The impedance as per Olin

(R1*R2)/(R1+R2) will decrease.

How will be the time to rise the signal on the capacitor from 0V to
2.99V in the case of 2.95K bottom resistor compared to the rise time
when the bottom resistor is 3.0K??

Will it decrease as per Olin's proposition  - the lower impedance -
the higher speed of signal?
***

2009\10\05@152809 by Michael Rigby-Jones

flavicon
face


> -----Original Message-----
> From: RemoveMEpiclist-bouncesKILLspamspammit.edu [piclist-bouncesSTOPspamspamspam_OUTmit.edu] On
Behalf
{Quote hidden}

Are you genuinely failing to understand what people are trying to
explain, or are you now trolling?

1) With a 5v signal, and a potential divider of 2k and 3k, the final
voltage will be 5 * 3/(2+3) = 3v.  The source impedance will be 3k||2k =
1.2k.  The 10%-90% voltages will be 0.3v-2.7v.

2) With a 5v signal, and a potential divider of 2k and 2.95k, the final
voltage will be 5 * 2.95/(2+2.95) = 2.98v.  The source impedance will be
2.95k||2k = 1.19k.  The 10%-90% voltages will be 0.298v-2.682v

Assuming both circuits are driving the same capacitive load the rise and
fall times will be slightly lower (faster) in the second case due to the
lower source impedance, but the voltage swing will be slightly lower as
well.  Do you now understand?  If not then I can recommend 'The Art of
Electronics' to gain a basic understanding of these principals.

Regards

Mike

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2009\10\05@160247 by Michael Rigby-Jones

flavicon
face


> -----Original Message-----
> From: spamBeGonepiclist-bouncesSTOPspamspamEraseMEmit.edu [KILLspampiclist-bouncesspamBeGonespammit.edu] On
Behalf
{Quote hidden}

The phase of the data and clock can indeed be adjusted programmatically,
but the requirements are set ONLY by the devices you are driving, not by
the solution which happens to give you the best rising and falling
edges.  If you set the incorrect phase then SPI devices will either not
work correctly or at all, or worse will work intermittently.

You seem to have this idea that the faster the edge the better, this is
far from the truth in the real word.  Fast edges can cause many problems
in circuits, so it's a good idea to have edges that are fast enough to
provide enough timing margin but not significantly faster.  If you need
faster edges than the purely resistive divider can achieve for a given
capacitive load, it's a simple matter to use a capacitor across the
upper resistor to provide a compensated divider.

As others have said, the rise and fall times of an edge are always
relative to the final value of the signal; typically you would quote the
10%-90% or 20%-80% time (and tell people which one you are using).  You
can't possibly use a fixed voltage as a reference; if you changed the
potential divider so the final voltage was less than 2.9v, this would
give a rise time of infinity by your definition.

Regards

Mike

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2009\10\06@082412 by olin piclist

face picon face
Marechiare wrote:
> How will be the time to rise the signal on the capacitor from 0V to
> 80% of 3.0V (that is 2.4V) in the case of 2.95K bottom resistor
> compared to the rise time when the bottom resistor is 3.0K?

Once again you are asking for the rise time to a fixed voltage, not a fixed
fraction of the steady state voltage.

Your problem statement was a 5V source driving a 2.000Kohm,3.000Kohm divider
with a capacitive load.  That means the steady state output is 3.000V.  If
we are measuring the rise time to 80%, then the threshold in that case is
2.400V.

If you change the bottom resistor to 2.950Kohms, then the steady state
voltage becomes 2.980V and the 80% threshold level therefore becomes 2.384V.
And yes, in the second case the result of a step input will reach the 80%
threshold (2.384V) a little quicker than it will reach the 80% threshold
(2.400V) in the first case.


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2009\10\06@085733 by Marechiare

picon face
Michael Rigby-Jones wrote:
> Are you genuinely failing to understand what people are trying to
> explain, or are you now trolling?
>
> 1) With a 5v signal, and a potential divider of 2k and 3k, the final
> voltage will be 5 * 3/(2+3) = 3v.  The source impedance will be 3k||2k =
> 1.2k.  The 10%-90% voltages will be 0.3v-2.7v.
>
> 2) With a 5v signal, and a potential divider of 2k and 2.95k, the final
> voltage will be 5 * 2.95/(2+2.95) = 2.98v.  The source impedance will be
> 2.95k||2k = 1.19k.  The 10%-90% voltages will be 0.298v-2.682v
>
> Assuming both circuits are driving the same capacitive load the rise and
> fall times will be slightly lower (faster) in the second case due to the
> lower source impedance, but the voltage swing will be slightly lower as
> well.  Do you now understand?  If not then I can recommend 'The Art of
> Electronics' to gain a basic understanding of these principals.

First, we are talking only about rising voltage on a capacitor, we ARE
NOT talking about how the capacitor will be DISCHARGED through the
resistors, please, re-read my previous post.

Second, let's refresh the scheme: we have a capacitor connected to
ground by one leg and through its other leg and resistor R1 getting
connected to DC source. Also there is a resistor R2 connected to the
capacitor IN PARALLEL. That second resistor _ALWAYS DISCHARGES the
capacitor, that is, tries to diminish the voltage on the capacitor,
you may call that resistor - leakage resistance.

How, the hell on the earth, lower R2 value, that is increase in
current leakage to ground from the capacitor would help the DC source
to charge the capacitor faster through the same constant resistor R1?
Lower R2 would mean lower impedance according to you.

2009\10\06@094122 by Spehro Pefhany

picon face
At 08:57 AM 10/6/2009, you wrote:
{Quote hidden}

I also would recommend _Art of Electronics_ -- it is aimed at those who
wish to get a quick grasp of electronics without delving too deeply into
theory and math (originally created for physics grad students who needed
to be able to quickly create useful scientific apparatus, AFAIUI). Of
course *some* math is required, but I don't think it goes much beyond
1st year Uni.

The current (2nd) edition is getting a bit long in the tooth (1989), but still
quite useful. Last I talked to Win, he was hard at work on the 3rd edition
which should be out Real Soon Now (it has been assigned an ISBN at least/
at last: 0521809266). When it is released, the prices of used 2nd editions
should drop.

Best regards,










>

2009\10\06@095029 by olin piclist

face picon face
Marechiare wrote:
> First, we are talking only about rising voltage on a capacitor, we ARE
> NOT talking about how the capacitor will be DISCHARGED through the
> resistors, please, re-read my previous post.

It doesn't matter since the two are symmetric.  We are assuming a perfect
voltage source, therefore 0 impedence, driving the input to the resistor
divider.

> How, the hell on the earth, lower R2 value, that is increase in
> current leakage to ground from the capacitor would help the DC source
> to charge the capacitor faster through the same constant resistor R1?

Because "faster" is in the context of the final steady state voltage, and is
not the same absolute value as you change the resistance.


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2009\10\06@134002 by Marechiare

picon face
{Quote hidden}

Still beyond my comprehension. This thread is about converting output
of 5V part to input of 3V part. Thus the 3V Vdd is fixed. The  part
CC1101 is fixed too. Its logic "1" input voltage is from VDD-0.7 to
VDD according to the datasheet (see 4.8 DC Characteristics, Table 17:
DC Characteristics). So the bottom logic "1" input voltage is fixed
too and is equal to 3V-0.7V=2.3V

What we can do is just slightly vary the divider's resistors, and see
how this would affect the time the rising voltage would reach that
2.3V. (That's it, we don't need discussing those 80% and introducing
other new rules like the divider ratio must be constant) .

That variations are exactly what I did in real life. For larger
variations of the divider's ratio I used Schottky diodes on inputs to
limit the input voltage (was within the specs for that parts). Within
these absolutely valid to OP's specs variations you can easily find a
pattern when the positive variation of impedAnce of the divider would
result in increase of rising speed, not in the decrease which
contradicts your statement: "lower impedance - higher speed".

2009\10\06@152235 by olin piclist

face picon face
Marechiare wrote:
> Still beyond my comprehension.

Yes, you really need to read up on this stuff.

> That's it, we don't need discussing those 80% and introducing
> other new rules like the divider ratio must be constant.

But we do, since that's what's needed to the circuit to work correctly.


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(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\06@162049 by Bob Blick

face
flavicon
face

On Tue, 6 Oct 2009 20:40:01 +0300, "Marechiare" <EraseMEmarechiarespamEraseMEgmail.com>
said:

> That variations are exactly what I did in real life. For larger
> variations of the divider's ratio I used Schottky diodes on inputs to
> limit the input voltage (was within the specs for that parts).

Resistor in series and Schottky diode clamp to the 3V supply? Be careful
about how much current it pumps into the 3V supply so as not to raise it
or hold the 3V circuit from reset on power up/down. Especially if you
have several pins to convert levels upon.

On another note, you guys seem to have picked ever so slightly different
ground to defend so the shots don't seem to be hitting anything
interesting. There also doesn't seem to be a lot of [PIC] going on.

Care to call a cease-fire until another hill is found to claim?

Thanks,

Bob

--
http://www.fastmail.fm - Or how I learned to stop worrying and
                         love email again

2009\10\06@163011 by Mark E. Skeels

flavicon
face

> On another note, you guys seem to have picked ever so slightly different
> ground to defend so the shots don't seem to be hitting anything
> interesting. There also doesn't seem to be a lot of [PIC] going on.
>
> Care to call a cease-fire until another hill is found to claim?
>
>
>
>  
:-)

Well put.

2009\10\08@145135 by Marechiare

picon face
Bob Blick wrote:
"Marechiare" said:
>> That variations are exactly what I did in real life.
>> For larger variations of the divider's ratio I used
>> Schottky diodes on inputs to limit the input voltage
>> (was within the specs for that parts).
>
> Resistor in series and Schottky diode clamp to the
> 3V supply? Be careful about how much current it
> pumps into the 3V supply so as not to raise it
> or hold the 3V circuit from reset on power up/down.
> Especially if you have several pins to convert levels upon.


Yeah, you are right, that's why I don't advocate the divider's
approach. Your concern about "how much current it pumps into the 3V
supply" you may address to those who advocate the divider's approach.
Was written by one of them:


On Mon, Oct 5, 2009 at 1:07 AM :
> On the other end, the highest high of 3.48V is only
> 250mV above the lowest possible Vdd.  There won't
> be any meaningful current thru any protection
> diode at 250mV.


Bob Blick wrote:
> On another note, you guys seem to have picked ever
> so slightly different ground to defend so the shots don't
> seem to be hitting anything interesting. There also
> doesn't seem to be a lot of [PIC] going on.

No, one point about PIC inputs with Schmitt triggers yet to be mentioned:

{Quote hidden}

This phrase (I removed typos) "The worst case logic high threshold is
therefore 3.37V * 0.8 = 2.7V"

The phrase could be misleading to many. My understanding how PIC
Schmitt triggers work is that high threshold 2.7V for Vdd 3.37V is the
BEST case, not the worst case (correct me if I'm wrong).

That is, from the very Schmitt Trigger idea it is guaranteed that the
level below 2.7V won't be considered logic "1". This means that logic
"1" won't be just >=2.7V. It could take much higher level to actually
reach logic "1".

So, the operating range of possible voltage that should be applied as
logic "1" shifts very closely to if not beyond the specs on max
voltage applied to inputs. Especially taking into account that the
system discussed involves RF module that, probably, would:
- surge supply chains destabilizing the LDO;
- cause gradient of potential on the ground lines;
- introduce RF induced voltages;
- etc etc;

Also should be taken into account that OP mentioned not 3.3V, but 3.0V
and the desire to explore the supply voltage down to 1.8V. This would
narrow the gaps even more.


> Care to call a cease-fire until another hill is found to claim?

Any ideas how to make it look like not a fire? I tried hard to stay
within reasonable rules this time. What should I correct in my
approach? Thanks.

2009\10\08@160622 by Bob Blick

face
flavicon
face

On Thu, 8 Oct 2009 21:51:33 +0300, "Marechiare" said:

> > Care to call a cease-fire until another hill is found to claim?
>
> Any ideas how to make it look like not a fire? I tried hard to stay
> within reasonable rules this time. What should I correct in my
> approach? Thanks.

If you're still enjoying the exchange, feel free to continue.
The [EE] tag is probably a better choice for long discussions about
resistors and fractions of a volt.
Other than that I see nothing to offend.

Cheerful regards,

Bob

--
http://www.fastmail.fm - Or how I learned to stop worrying and
                         love email again

2009\10\08@160714 by Marechiare

picon face
Michael Rigby-Jones wrote:
> You seem to have this idea that the faster the edge the
> better, this is far from the truth in the real word.  Fast
> edges can cause many problems in circuits, so it's a
> good idea to have edges that are fast enough to provide
> enough timing margin but not significantly faster.

There is no much sense attributing me this or that idea. I would
recommend you a good book "Art of Electronics" to figure out the
timings on your own.

The FET input capacitance is sort of some hundred pF. The PIC output
current is limited to 25ma. This would yield a transition time sort of
some tenths of nanoseconds, aprox 10 to 20 times faster than the
divider's timing. Such a slope corresponding to aprox 10MHz sine at a
fraction of mA current should not cause much trouble.


> If you need faster edges than the purely resistive divider
> can achieve for a given capacitive load, it's a simple
> matter to use a capacitor across the upper resistor to
> provide a compensated divider.

If it were me who had expressed that overgeneralized statement, I'd
possibly had been experienced severe ostracism by some for spreading
out bad practices :-)

2009\10\08@163327 by olin piclist

face picon face
Marechiare wrote:
> That is, from the very Schmitt Trigger idea it is guaranteed that the
> level below 2.7V won't be considered logic "1".

No, read the datasheet again.  The signal is guaranteed to be interpreted as
high if it exceeds 80% of Vdd.


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(978) 742-9014.  Gold level PIC consultants since 2000.

2009\10\09@041859 by Marechiare

picon face
>> That is, from the very Schmitt Trigger idea it is guaranteed
>> that the level below 2.7V won't be considered logic "1".
>
> No, read the datasheet again.  The signal is guaranteed to
> be interpreted as high if it exceeds 80% of Vdd.

I did read the datasheet before. It says min logical high is 80% of
Vdd. I did find no clause that it guarantees any level higher to be
interpreted as high; nor find I a clause that levels below 80% of Vdd
are guaranteed not to be interpreted as high.

I used to think that since the feature the Schmitt Trigger is all
about is its hysteresis, and no any other voltages are mentioned, then
that MIN/MAX values are about the hysteresis, that is, the signal
within the "dead range" won't affect theTrigger state. Perhaps I was
wrong, I'll re-check it later.

If hysteresis is unspecified or even is absent, - this won't be a
problem for SDO or SS lines, but for slowly rising/falling SCK (due to
divider's resistors) this may cause "level bouncing" near the point
when logical "0" level starts to be interpreted as high. A significant
load on 5V LDO at the moment would cause (a divider's voltage/input
signal) to "fall back" slightly and  the logic "1" would get back to
"0" for a moment.  Some desing arrangements should be taken to avoid
the effect.

2009\10\09@085201 by olin piclist

face picon face
Marechiare wrote:
> I did read the datasheet before. It says min logical high is 80% of
> Vdd.

I just looked at the 18F2520 datasheet, DS39631E, as a example.  On page 335
in the section "Input High Voltage", it specifies parameter D041 "with
Schmitt trigger buffer" to have a min/max range of 0.8 Vdd to Vdd.

On a 5V system therefore, any input voltage from 4.0V to 5.0V is guaranteed
to be interpreted as a logic high.

> I did find no clause that it guarantees any level higher to be
> interpreted as high;

Actually that's exactly what it's saying.  Read it again.


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2009\10\09@110733 by Michael Rigby-Jones

flavicon
face


> -----Original Message-----
> From: @spam@piclist-bounces@spam@spamspam_OUTmit.edu [spamBeGonepiclist-bouncesspamKILLspammit.edu] On
Behalf
{Quote hidden}

YES!!! Finally we are getting somewhere; lowering R2 DOES reduce the
source impedance.  I guess you took the advice to read up on Thevenin's
theorem?

Regards

Mike

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2009\10\09@111949 by Harold Hallikainen

face
flavicon
face

> If hysteresis is unspecified or even is absent, - this won't be a
> problem for SDO or SS lines, but for slowly rising/falling SCK (due to
> divider's resistors) this may cause "level bouncing" near the point
> when logical "0" level starts to be interpreted as high.

Years ago I had problems with a rather long SPI bus that was driving a
PLD. The PLD was real fast and would detect ringing on the SPI clock line
causing the SPI data to occasionally be off by a bit.

On using voltage dividers as level translators (5V to 3.3V), the use of
low resistor values is an attempt to present a low Thevenin resistance to
the 3.3V side so capacitive loading does not slow the edge too much. An
idea I mentioned before, though, would be to put a small capacitor across
the top resistor so we have a resistive divider in parallel with a
capacitive divider. This is just like scope probe compensation and should
eliminate the slow edge due to voltage divider resistance.

However, as the parts count goes up, I'm real tempted to just buy a level
translator chip. Especially if there are several lines to be translated.

Harold




--
FCC Rules Updated Daily at http://www.hallikainen.com - Advertising
opportunities available!

2009\10\09@132158 by Marechiare

picon face
{Quote hidden}

Yes, I meant "ringing on the SPI clock line causing the SPI data to
occasionally be off by a bit."

In my opinion a small capacitor across the top resistor will introduce
new problems, and won't solve the main problem: the voltage is
constructed on the sender side, not on recipient's side.

Why not just drain current to ground on the sender side by open
collector or open drain. Then on recipient's side the current would
create a voltage on a resistor connected to recipient's Vdd.

Open collector or open drain can only drain current, not inject it to
the resistor/input capacitance. Thus you are guaranteed the voltage on
the input (relative to Vdd)  would only increase in abs value
regardless of voltage disturbances along the bus. There will be no
"ringing" on the input. Just sense the input signal relative to
recipient's Vdd.


> However, as the parts count goes up, I'm real tempted to just buy a level
> translator chip. Especially if there are several lines to be translated.

They may not work well for a long bus as they only translate voltage,
they don't "drain "current.

2009\10\09@132708 by Marechiare

picon face
Michael Rigby-Jones wrote:
> I guess you took the advice to read up on Thevenin's
> theorem?

How is your question connected to this thread?

2009\10\09@140321 by olin piclist

face picon face
Marechiare wrote:
> They may not work well for a long bus as they only translate voltage,
> they don't "drain "current.

I smell a dead fish being waved.


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2009\10\09@150441 by Marechiare

picon face
>>> However, as the parts count goes up, I'm real tempted to just buy a level
>>> translator chip. Especially if there are several lines to be translated.
>>
>> They may not work well for a long bus as they only
>> translate voltage, they don't "drain "current.
>
> I smell a dead fish being waved.


Bon appetit.

Level translators are not the same as bus drivers in context of the
discussed long bus. I said to "drain" current to ground on a sender
side. Another option is to source current from power supply on the
sender side.

2009\10\10@073123 by Marechiare

picon face
I wrote:
> They may not work well for a long bus as they only ,
> translate voltage they don't "drain "current.

Yes, indeed, the phrase written in a hurry looks somewhat strange.
Should be re-written as: "A level translator chip may not work well on
a long bus".

2009\10\24@141223 by Kevin

picon face
On Mon, 28 Sep 2009, Kevin wrote:

Just as an FYI by the time I got done porting the C code to
work with the CC1101 chip all the 3.3 volt parts came in.
So I  have my project working with a PIC16LF87 with
bootloader, MAX3222 and the CC1101 chip from TI.
I think it is a pretty good set-up for about $15.

Regards,
Kevin

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