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'[PIC] SPI bus conflicts. Please help!'
2005\10\18@002156 by James James

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Hi,
I need three PICs to communicate with each other via
SPI bus.  I setup one as a SPI Master and the other
two as SPI Slaves.

The communication was fine with 1 Master and 1 Slave
until I connect the second Slave to the SPI bus .  I
think the problem is related to the SDO signal of the
two slaves.  When the SPI Master wants to talk to the
second Slave, because the SDI signal of the Master is
held either high or low by the first Slave, the second
slave cannot toggle the SDO pin (since they are tied
together at the Master's SDI pin).

I tried to sum the two SDO signals of the two Slaves
via 1K resistor, but the comm is still intermittent.
Is there other anyway around this?  Thanks!
Best regards,




       
               
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2005\10\18@003121 by D. Jay Newman

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> I tried to sum the two SDO signals of the two Slaves
> via 1K resistor, but the comm is still intermittent.
> Is there other anyway around this?  Thanks!
> Best regards,

I use 10k resisters for pull-ups and have not had such problems.
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2005\10\18@005134 by James James

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I tried the 10k pull up resistor, it doesn't help.  

Additional info: I have SS pin enabled on both slaves

--- "D. Jay Newman" <.....jayKILLspamspam@spam@sprucegrove.com> wrote:

{Quote hidden}

> --

2005\10\18@012132 by D. Jay Newman

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> I tried the 10k pull up resistor, it doesn't help.  
>
> Additional info: I have SS pin enabled on both slaves

By enabled, do you mean +5V?

The SS pin *must* be low on one and only one of the slaves.

You must also put both the slave devices in a mode where they
listen to the SS (Slave Select) pin.

{Quote hidden}

2005\10\18@072926 by olin piclist
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James James wrote:
> Additional info: I have SS pin enabled on both slaves

You obviously know enough to know this is an issue, so I don't understand
why you didn't fix this first.


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2005\10\18@163243 by James James

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Hello,
I think you misunderstood me.  I meant the SS *feature* is enabled on both slaves.  The master doesn't take the SS signal low on both slaves at the same time.

The communication seems to be much improved by inserting a delay in between the communication of the two slaves (see step 4 below), like this:

1. Slave1 CS Low
2. Send Data
3. Slave1 CS High
4. *DELAY for 10ms*
5. Slave2 CS Low
6. Send Data
7. Slave2 CS High




I am guessing when Slave1 CS in step 4 goes high, it needs some times to make its SDO pin high impedance.  That's why the delay helps, but I could be wrong?

Regards,

Olin Lathrop <olin_piclistspamspam_OUTembedinc.com> wrote:
James James wrote:
> Additional info: I have SS pin enabled on both slaves

You obviously know enough to know this is an issue, so I don't understand
why you didn't fix this first.


*****************************************************************
Embed Inc, embedded system specialists in Littleton Massachusetts
(978) 742-9014, http://www.embedinc.com

2005\10\18@164514 by Jan-Erik Soderholm

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James James wrote :

> I am guessing when Slave1 CS in step 4 goes high, it needs
> some times to make its SDO pin high impedance...

That would defenitely be a parameter that I'd expect
to be clearly spelled out in the data sheet...

Jan-Erik.



2005\10\19@062908 by PY2NI TERRA

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   Just a thought I don´t have experience with SPI but, a bunch of weird
things happen when you forget pull up resistors on a I2C bus, perhaps you
need some of them to help the rising/falling (pull down) time of the SPI
bus.

Horta


{Original Message removed}

2005\10\19@100303 by Thomas C. Sefranek

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-----Original Message-----
From: @spam@piclist-bouncesKILLspamspammit.edu [KILLspampiclist-bouncesKILLspamspammit.edu] On Behalf Of
James James
Sent: Tuesday, October 18, 2005 4:16 PM
To: Microcontroller discussion list - Public.
Subject: Re: [PIC] SPI bus conflicts. Please help!

Hello,

The communication seems to be much improved by inserting a delay in between
the communication of the two slaves (see step 4 below), like this:

1. Slave1 CS Low
2. Send Data
3. Slave1 CS High
4. *DELAY for 10ms*
5. Slave2 CS Low
6. Send Data
7. Slave2 CS High


I am guessing when Slave1 CS in step 4 goes high, it needs some times to
make its SDO pin high impedance.  That's why the delay helps, but I could be
wrong?

Regards,



I can't seem to imagine why you need a delay.
I "do" one SPI master to 12, 24 and 48 slaves with no delays (well a few
machine cycles) between selecting the slave.  I guess I would have to know
more of the details of your implementation.  E.G. Which mode?  IRQs?

BTW:  I have yet to see any Microchip PIC with all SPI modes and Slave Sync
pin Working.  You WILL get an interrupt even if the slave is NOT selected.
You WILL get collisions using Slave Sync. With some modes.  I had hoped they
Fixed this in the 18F versions, but alas, despite their promises, no joy.

Tom

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2005\10\19@210821 by Dmitriy Kiryashov

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Interesting approach indeed... :) Impedance match line termination.
What was the SPI frequency discussed ? Probably 200 MHz or higher.

Seriously there is nothing difficult about SPI running at 10 MHz.
If device is too slow to switch on and off by slave select additional
digital multiplexer(s) can be used to switch multiple data lines pretty fast.


Dmitriy.


>     Just a thought I don´t have experience with SPI but, a bunch of weird
> things happen when you forget pull up resistors on a I2C bus, perhaps you
> need some of them to help the rising/falling (pull down) time of the SPI
> bus.
>
> Hort

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