Hey,
you can find the datasheet for the 24LC16 here: http://ww1.microchip.com/downloads/en/DeviceDoc/21703E.pdf
The A2...A0 pins allow to communicate with up to eight 24LC16 devices, all connected to the same I²C bus. Addressing of the devices is performed by sending a control byte via the bus.

The control byte is composed by the fixed bits 1010, followed by three address bits, followed by the read/*write bit. A 24CL16 with all three address pins connected to Vss would acknowledge the control byte 1010000x, and one with A0 connected to Vcc and A1, A2 connected to Vss would acknowledge the control byte 1010001x, etc. As long as you only have one EEPROM on the bus, simply connect all address pins to Vss, and send 1010000x as the control byte.

Gunther,
Page 11 of said datasheet states that A0, A1, and A2 are not connected in this device.  This would indicate to me that the chip address feature of IC2 cannot be used with this device.  Please correct me if I'm wrong.

This doesn't mean that you couldn't use more than 1 chip, simply that you cannot use the multiple IC2 address protocall.  You could use a decoder chip and wrtie some code that would select the proper memory chip.

Nate,
this is strange. I did not use the 24LC16 so far but "smaller" devices, like the 24LC02. In these datasheets they also state that the address pins are not connected. But I could successfully verify that the chips decode the status of the address pins. Although, I'm using 24LC02s made by ST and not by Microchip. Maybe, this explains the difference.

On the other hand, on page 6 where the control byte is explained, they say that the three bits in the control byte are used to select one of the eight 256 word blocks of the memory. As the address following the control byte is only 8 bits wide, three additional bits are required to cover the fill address space of 2048 bytes. Seems as if there actually can only be one 24LC16 on a bus.

Perhaps you consider using 24LC64 chips instead. They definitely allow for eight devices on a bus, and they have two address bytes following the control byte in order to address the full range of the memory. In the end, this solution my be even cheaper as one 24LC64 replaces four 24LC16 chips, and there is no need for some "tricky" decoding. I use the 24LC64 in some of my SX applications with no problems.

Nate,
I was just curious, and got the ST datasheet for their 24C01...16 EEPROMs from http://www.st.com/stonline/products/literature/ds/5067/m24c16-w.pdf. Their 01 and 02 devices actually have the three address bits decoded, the 04 device has two bits decoded, the 08 device just one, and the 16 device none at all. Where none of the Micochip equivalents do address decoding at all.

So that means, not only is it limited to only one of those devices, but only one of any device, right?  Let's say I have an sx set up as a slave on that same bus, and i would like to send some info to only the sx, I could set the address to some abritrary number, but the eeprom would answer to any address, correct?  So it would be getting all of the bytes sent to it also.  I realise that i could probably set the write protect pin of the eeprom, but i would rather just get a different chip.  I am looking to have possible 4 sx's set up as slaves, and 1 eeprom and one rtc all set up on the same i2c bus (if thats possible).  Thanks for your help!

John,
fortunately, this is not the case. The first four bits in the EEPROM's control word are 1010, so let your slave SXes just decode some other bit pattern that is unique on the bus, i.e. not decoded by any other device plus three bits with patterns unique to each SX, for example 1111000x 1111001, 1111010, up to 1111111x, and you can have eight SXes acting as slaves on the bus when the master sends a control byte starting with 1111 in this example. The EEPROM will not answer because it only "listens" to commands starting with 1010.

A while ago, I have developed a system similar to this with up to 5 SXes on one bus. In this system, each of the SXes could act as master and slave, therefore I also had to handle bus arbitration but it worked nicely in the end.

John,
The bottom line is: If you want to use an IC2 bus with more than one device (SX or EEPROM) and use the defined IC2 protocall, all the devices on the bus need to be able to decode the address part of the IC2 protocall.  Using the write protect pin of the memory will not prevent the memory from distorting bus data when a slave SX is asked to do a read function.

From Gunther's ST information, you could have maximum (4) 2KB EEPROM devives and (4) slave SX devices on the same bus using strictly the IC2 protocall (which only gives you 8KB of memory).

An alternative would be to use the IC2 protocall, but have 2 busses.  This obviously will take a little more work the coding department.

Just out of curiosity, why so many SX slaves?

Beautiful!  That sounds great.  Thanks guys!