Good thought, I'm not sure if it's that or power dissipation or ??? -
they're all sort of the same thing <G> Well, we'll see.
Mark
M. Adam Davis wrote:
{Quote hidden}>
> Likely it has to deal with the power bus size going to those ports. Vdd
> & Vss have to get to the port somehow, and beefy power busses take up a
> good chunk of space on the die.
>
> -Adam
>
> Mark Willis wrote:
> >
> > I tried to sent this to my Microchip FAE; Apparently he's not with
> > Microchip any more. Need to call & find a new FAE, or just ask the
> > PICList <G>
> >
> > ---
> >
> > I have always sort of wondered, but not asked yet.
> >
> > Why is there a "per-port" limit on current on various PICs?
> >
> > I'd guessed that the output drivers are all close enough together that
> > too much power off any one port would cause problems i.e. all FETs would
> > heat and "act up", but have never asked, just wanted to know for
> > certain.
> >
> > Mark
> >
> > --
> > I re-ship for small US & overseas businesses, world-wide.
> > (For private individuals at cost; ask.)
--
I re-ship for small US & overseas businesses, world-wide.
(For private individuals at cost; ask.)
