Post by thread:N-Flop: Re: QUIZ MASTER ( Who is the first?)

Perhaps not everyone has seen an N-Flop circuit. They're real cute. An R-S flop can be two cross coupled 2 input NAND gates one of the inputs is the control pin (R or S) the other feeds back the output of the OTHER NAND gate. A N-Flop has N N input NAND gates: 1 pin is again the control input for each gate and the other N-1 inputs feeds back the outputs of the other N-1 gates. This uses lots of parts by modern standards but are internally used in processors to do just the function of the quiz master: i.e one (ONLY) of several inputs without priority relationship. I think I saw a discrete implementation in a CDC6400 computer .. They often happen in interrupt circuits to vector to only one interrupt loc. but without priortisation (and possible lockout). The analog (analog!!) of this is often faster and uses less silicon. R.Martin > I just remembered: the R-S flipflop variant on this was called an 'N-flop' > works on the same principle.