Post by thread:Of anlalyzers and oscilloscopes.

I have been following the discussion on scopes on the PICLIST. spam_OUTMultiAnalyserTakeThisOuTyahoogroups.com is the off-shoot group discussing developing a Multianalyzer, ie an oscilloscope and logic analyzer. In the meantime, I had another look at my Spartan-3 development board that I bought. <http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3-CPLD-DK> I have decided to develop a (rudimentary) logic analyzer with it. It includes a Spartan-3 FPLA (200,000 gate) with a 50MHz clock, 2 x 256k x 16 SRAM, and RS232, PS/2 mouse/keyboard and VGA ports, 4 buttons, 8 slide switches, and 4 digits of 7-segment. They include a demo with a 640x480 VGA display with 8x8 characters of 16 colours with a PicoBlaze microprocessor core implementation. My plan is to suck 16 channels of digital data into the SRAM with the FPGA hardware and then display it to VGA with the microprocessor core, and use the pushbuttons/switches for a UI. Now my questions: 1. Should I sample at some suitable sample rate (<50MHz) directly into the (up to) 512k x 16 SRAM? Display would be to scan through the array and plot the results into VGA RAM. 2. Should I sample at 50 MHz and save the time of the transitions into (up to) 256k x 32 SRAM? 3. Should I implement triggers (or cursors) in software, indicating where they are by pattern matching . Conversely, 1-8 triggers could be implemented in hardware, using 1-4 bits to indicate the active cursor. 4. How are glitches usually handled? It would appear #2 would pick these up. 5. Drawing the display might be slow -- could be implemented in hardware, too. Anyway, I figure its a good project to learn VHDL :-) -- the demo already blinky de lights. Any words of advice or ideas would be welcome :-) David PS- perhaps with the addition of a front end and a coupla ADCs, it could become an oscilloscope, too. It is possible to increase the clock rate with another crystal, as it has a socket for this.

I have been following the discussion on scopes on the PICLIST. .....MultiAnalyserKILLspam@spam@yahoogroups.com is the off-shoot group discussing developing a Multianalyzer, ie an oscilloscope and logic analyzer. In the meantime, I had another look at my Spartan-3 development board that I bought. <http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3-CPLD-DK> I have decided to develop a (rudimentary) logic analyzer with it. It includes a Spartan-3 FPLA (200,000 gate) with a 50MHz clock, 2 x 256k x 16 SRAM, and RS232, PS/2 mouse/keyboard and VGA ports, 4 buttons, 8 slide switches, and 4 digits of 7-segment. They include a demo with a 640x480 VGA display with 8x8 characters of 16 colours with a PicoBlaze microprocessor core implementation. My plan is to suck 16 channels of digital data into the SRAM with the FPGA hardware and then display it to VGA with the microprocessor core, and use the pushbuttons/switches for a UI. Now my questions: 1. Should I sample at some suitable sample rate (<50MHz) directly into the (up to) 512k x 16 SRAM? Display would be to scan through the array and plot the results into VGA RAM. 2. Should I sample at 50 MHz and save the time of the transitions into (up to) 256k x 32 SRAM? 3. Should I implement triggers (or cursors) in software, indicating where they are by pattern matching . Conversely, 1-8 triggers could be implemented in hardware, using 1-4 bits to indicate the active cursor. 4. How are glitches usually handled? It would appear #2 would pick these up. 5. Drawing the display might be slow -- could be implemented in hardware, too. Anyway, I figure its a good project to learn VHDL :-) -- the demo already blinky de lights. Any words of advice or ideas would be welcome :-) David PS- perhaps with the addition of a front end and a coupla ADCs, it could become an oscilloscope, too. It is possible to increase the clock rate with another crystal, as it has a socket for this.