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I tried to reply before, but the list server bounced it back because the
message exceeded 1000 lines. Here it is again with the PICPRG.INS.PAS
attachment omitted:
{Quote hidden}> > > I don't remember exactly which chip it was, but I do remember that the
> > > Vpp/Vdd order mattered for it. One of the symptoms was that
> > > the ID word
> > > would sometimes come back all zero. I experimented enough to
> > > see positive
> > > evidence that the Vpp/Vdd order can be important.
> >
> > Do you recall whether this applied to a flash or EPROM/OTP PIC?
>
> It was definitely a flash chip because that's all I've tested so far. I
> think I was testing a 16F876 which requires Vdd before Vpp with an
algorithm
{Quote hidden}> that was the other way around. The result was flakiness. It would
> sometimes not appear to respond to commands at all by not driving the data
> line when expected. Other times is would drive the data line, but the ID
> word would read back all zeros.
>
> This caused me to put a special check into the algorithm that tries to
> identify the target chip. If the ID is 0, then switch to Vdd before Vpp
> reset and try again. Attached is PICPRG_ID.PAS, which is the host source
> code for the ID determination. I have also attached PICPRG.INS.PAS which
> might help you guess what some of the calls do.
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