The notation `op8` denotes either `A`, `B`, `C`, `D`, `E`, `H`, `L`, `IXH`, `IXL`, `IYH`, `IYL`, `(HL)`, `(IX+n)`, `(IY+n)` or a 8-bit immediate (constant).

This section includes all the instructions that perform basic mathematical operations.

Syntax: `add a,op8`

(8 bits) or `add reg16,reg16`

(16 bits), where you can use the following combinations (the first operand is on the left column):

BC | DE | HL | IX | IY | SP | |

HL | X | X | X | X | ||

IX | X | X | X | X | ||

IY | X | X | X | X |

The value of the two operands is added together, and the result is written back to the first one. In the case of 8-bit additions the `N` flag is reset, `P/V` is interpreted as *overflow*. The rest of the flags is modified by definition. On the other hand, 16-bit additions preserve the `S`, `Z` and `P/V` flags, and `H` is undefined. For example, if the result is out of the range (8 or 16 bits depending on the first operand), the `carry` flag is set.

Syntax: `sub op8`

The value of the operand is subtracted from `A`, and the result is also written back to `A`. The `N` flag is set, `P/V` is interpreted as *overflow*. The rest of the flags is modified by definition. There is no 16-bit version.

Syntax: `adc a,op8`

(8 bits) or `adc hl,reg16`

(16 bits, reg16 can be `BC`, `DE`, `HL` or `SP`)

The sum of the two operands plus the `carry` flag (0 or 1) is calculated, and the result is written back into the first operand. The `N` flag is reset, `P/V` is interpreted as *overflow*. The rest of the flags is modified by definition. In the case of 16-bit addition the `H` flag is undefined.

Syntax: `sbc a,op8`

(8 bits) or `sbc hl,reg16`

(16 bits, reg16 can be `BC`, `DE`, `HL` or `SP`)

The sum of the second operand and the `carry` flag (0 or 1) is subtracted from the first operand, where the final result is written back as well. The `N` flag is set, `P/V` is interpreted as *overflow*. The rest of the flags is modified by definition. In the case of 16-bit subtraction the `H` flag is undefined.

Syntax: `inc op8`

(immediate values are of course invalid) or `inc reg16`

(reg16: BC, DE, HL, IX, IY or SP)

Increments the value of the operand by one. 8-bit increments preserve the `C` flag, reset `N`, treat `P/V` as *overflow* and modify the others by definition. 16-bit increments *do not alter any of the flags*.

Syntax: `dec op8`

(immediate values are of course invalid) or `dec reg16`

(reg16: BC, DE, HL, IX, IY or SP)

Decrements the value of the operand by one. 8-bit decrements preserve the `C` flag, set `N`, treat `P/V` as *overflow* and modify the others by definition. 16-bit decrements *do not alter any of the flags*.

This instruction has no operands. When it is executed, the value in `A` is multiplied by -1 (two's complement). The `N` flag is set, `P/V` is interpreted as *overflow*. The rest of the flags is modified by definition. This instruction is completely equivalent to `cpl a`

followed by `inc a`

(both in execution time and in size).

Decimal Adjust Accumulator; no operands are needed. When this instruction is executed, the `A` register is BCD corrected using the contents of the flags. The exact process is the following: if the least significant four bits of `A` contain a non-BCD digit (i. e. it is greater than 9) or the `H` flag is set, then $06 is added to the register. Then the four most significant bits are checked. If this more significant digit also happens to be greater than 9 or the `C` flag is set, then $60 is added. If this second addition was needed, the `C` flag is set after execution, otherwise it is reset. The `N` flag is preserved, `P/V` is *parity* and the others are altered by definition.

These are the instructions that perform bit-level manipulation.

Syntax: `or op8`

Performs bit-wise OR between `A` and the operand, and writes the result back to `A`. The `C` and `N` flags are cleared, `P/V` is *parity*, and the others are altered by definition. An example:

```
%00101110
%10011101 i. e. only two zeroes give zero, all the other combinations result in one
---------
%10111111 (result)
```

Syntax: `and op8`

Performs bit-wise AND between `A` and the operand, and writes the result back to `A`. The `C` and `N` flags are cleared, `P/V` is *parity*, and the others are altered by definition. An example:

```
%00101110
%10011101 i. e. only two ones give one, all the other combinations result in zero
---------
%00001100 (result)
```

Syntax: `xor op8`

Performs bit-wise XOR (exclusive or) between `A` and the operand, and writes the result back to `A`. The `C` and `N` flags are cleared, `P/V` is *parity*, and the others are altered by definition. An example:

```
%00101110
%10011101 i. e. inequality gives one, while equality gives zero as a result
---------
%10110011 (result)
```

This instruction has no operands. It gives the one's complement of `A`, i. e. all the bits of `A` are reversed individually. It sets the `H` and `N` flags, and leaves the others intact.

Syntax: `set n,op8`

(n is a number between 0 and 7, `op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

As its name suggests, this instruction sets the n^{th} bit of the operand given. The flags are preserved.

Syntax: `res n,op8`

(n is a number between 0 and 7, `op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

The instruction resets the n^{th} bit of the operand given. Again, the flags are preserved.

This is the "Set Carry Flag"instruction, which simply alters the flags. Besides setting the `C` flag, it clears `H` and `N` as well.

"Complement Carry Flag”, i. e. negating the `C` flag. Besides, `N` is cleared and `H` holds an undefined value after execution.

This set of instructions does binary shifting, which is equivalent to multiplications and divisions with (powers of) 2. Rotations also belong to this group.

Syntax: `sla op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

The bits of the operand are shifted leftwards, bit 0 (the least significant bit) is reset. The bit leaving the operand on the left appears in the `carry`. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `sra op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

The bits of the operand are shifted rightwards, except for bit 7 (the most significant bit), whose value is left intact (the sign is preserved). The bit leaving the operand on the right appears in the `carry`. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `sll op8`

or `sl1 op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

*This instruction is undocumented, and incompatible with the subsequent generations of the CPU (e. g. the Z380 does not support it), therefore you should avoid using it. However, it should work on every Z80 processor.* The bits of the operand are shifted leftwards, bit 0 is set to one. The bit leaving the operand on the left is lost. The `C`, `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `srl op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

The bits of the operand are shifted rightwards, bit 7 is reset. The bit leaving the operand on the right appears in the `carry`. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `rl op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

9-bit rotation to the left. The bit leaving on the left is copied into the `carry`, while the old value of the `carry` appears in bit 0 of the operand. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `rr op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

9-bit rotation to the right. The bit leaving on the right is copied into the `carry`, while the old value of the `carry` appears in bit 7 of the operand. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

There are no operands to this instruction. It is the same as `rl a`

except that it is faster and does not change the `S`, `Z` and `P/V` flags.

There are no operands to this instruction. It is the same as `rr a`

except that it is faster and does not change the `S`, `Z` and `P/V` flags.

Syntax: `rlc op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

8-bit rotation to the left. The bit leaving on the left is copied into the `carry`, and to bit 0 of the operand as well. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

Syntax: `rrc op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

8-bit rotation to the right. The bit leaving on the right is copied into the `carry`, and to bit 7 of the operand as well. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition.

There are no operands to this instruction. It is the same as `rlc a`

except that it is faster and preserves the `S`, `Z` and `P/V` flags.

There are no operands to this instruction. It is the same as `rrc a`

except that it is faster and preserves the `S`, `Z` and `P/V` flags.

This instruction has no operands. It is a 4-bit leftward rotation of the 12-bit number whose 4 most significant bits are the 4 least significant bits of `A`, and its 8 least significant bits are in `(HL)`. I. e. if `A` contains `%aaaaxxxx`

and `(HL)` is `%yyyyzzzz`

initially, their final values will be `A`=`%aaaayyyy`

and `(HL)`=`%zzzzxxxx`

. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition. The `carry` flag is preserved.

This instruction has no operands. It is a 4-bit rightward rotation of the 12-bit number whose 4 most significant bits are the 4 least significant bits of `A`, and its 8 least significant bits are in `(HL)`. I. e. if `A` contains `%aaaaxxxx`

and `(HL)` is `%yyyyzzzz`

initially, their final values will be `A`=`%aaaazzzz`

and `(HL)`=`%xxxxyyyy`

. The `H` and `N` flags are reset, `P/V` is *parity*, `S` and `Z` are modified by definition. The `carry` flag is preserved.

The following instructions are used to verify data and store the results in the flags.

Syntax: `cp op8`

This is a virtual subtraction from `A`, without writing back the result. You can regard it as a `sub op8`

that affects only the flags. The most important examples: if `A` = `op8` then the `C` flag is reset, and `Z` is set. If `A` < `op8`, `C` is set and `Z` is reset. If `A` > `op8` then both `C` and `Z` are reset.

Syntax: `bit n,op8`

(`op8` cannot be immediate, `IXH`, `IXL`, `IYH` or `IYL`)

The *opposite* of the n^{th} bit of the second operand is written into the `Z` flag. The `carry` is left intact, `N` is reset, `H` is set, while `S` and `P/V` are undefined.

There are no operands. This is a `cp (hl); inc hl; dec bc`

combined in one instruction. The `carry` is *preserved*, `N` is set and all the other flags are affected as defined. `P/V` denotes the *overflowing* of `BC`, while the `Z` flag is set if `A`=`(HL)` at the time of the comparison.

The same as `cpi`

but with `HL` being *decremented*.

Simply `cpi`

repeated until either `BC` becomes zero or `A` is equal to `(HL)`.

The only difference from `cpir`

is that `HL` is decremented during each iteration.

file: /Techref/zilog/z80/app1b.htm, 15KB, , updated: 2018/11/6 17:43, local time: 2024/5/29 17:11, |

©2024 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?<A HREF="http://massmind.org/techref/zilog/z80/app1b.htm"> Z80 Assembly</A> |

Did you find what you needed? |

## Welcome to massmind.org! |

## Welcome to massmind.org! |

.