prev: pwb_design_flow.htm -- next: PWB_release.htm updated 2003-08-07
libraries of schematic symbols and layout footprints
see also Making your own symbols #symbols , and making your own footprints #footprint .
Vounteers have donated footprints at http://opencircuits.com/PCB_Footprints .
Brian Guralnick has generously donated a library with both "schematic components" and "PCB footprints" ("land patterns") at ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/BHGlibs.zip [FIXME: has moved elsewhere ?] and ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/SuperCompact.zip "all schematic discrete components are optimized for the schematic capture display. They are super compact. The pcb foot prints are also space optimized." ``Except for double diodes, discrete component pinouts are B,S,E, G,S,D, A,K instead of pin numbers for matching footprints within your own footprint libraries.''
Protel keeps putting updated parts libraries on its web site: Protel Libraries http://www.protel.com/resources/libraries/ /* was http://www.protel.com/library/ */ and http://www.protel.com.au/resources/libraries/ /* was http://www.protel.com.au/library/index.html */ and http://www.protel.com/news.htm /* was http://www.protel.com/library/qa/whats_new.html */ .
a free library of footprints and symbols (which they call ``decals''): http://www.cadprosystems.com/ (is this compatible with Protel ?)
Q: What's the quickest way to print a page that lists *all* the footprints of a pcb library ? Looking at a page full of footprints at once is much faster than scrolling through the library looking at one at a time. (Especially with several pcb libraries full of parts).
A: "Geoff Harland" on 2001-05-24 08:39:28 PM writes: (lightly edited by the FAQ maintainer):
There's several different things you can do at this point.
If you print just the Drill Drawing layer, the printout will index and count the usage of each hole size used.
Q: Which footprint should I use ?
A: Unlike through-hole components, there is no One True Footprint for a SMT part.
My understanding is that IPC footprints are (were ?) optimized for (c) wave soldering, so many people use smaller footprints that work fine for their process (a) or (b).
There is a (free) online land pad calculator from IPC, http://www.ipc.org/html/fsresources.htm .
Bugs in the Protel footprint library (Have these been fixed already ?)
(schematic library design tips for making new symbols.)
If you want a symbol that's not already in the schematic symbol libraries , then you must make it yourself in your own library.
When designing a new schematic symbol, Ian Wilson says: "don't use hidden pins ... ever. The are not logical or intuitive and new users consistently have problems with them."
There seem to be 2 kinds of schematic symbols:
When making a new shematic symbols, it helps to
(The pin "numbers" on the schematic symbol must match up with corresponding "numbers" on the PWB footprint. The pin "names" on the schematic are just for documentation.)
Bug: The "update schematic" button really ought to (1) take the version of the part in memory (which you have just edited) and save it to disk, *then* (2) use the version on disk to update open schematics.
But at the moment, it only does step (2).
Workaround: Always ``press the "file save" button before you press the "update schematic" button.'' -- "Graeme Zimmer" on 2001-04-04 05:38:42 PM
Q: How do I copy a schematic symbol from some other library to my own personal schematic symbol library ?
A: After I right-click on the name of the component (in the left pane of the symbol editor), I choose "copy". No more clicks needed. Then I switch to my own personal libraries, right-click in that left pane, and choose "paste". Don't have to click again here either. In the schematic symbol editor, there's no way to do that from the menu options -- you *must* do it with the right-click thing. I wish for a ``Edit | Copy Component'' and a ``Edit | Paste Component''. Unfortunately, the ``Tools | Copy Component...'' does *not* do the right thing. Then rename it.
If the footprint you want isn't already in the libraries , then you'll have to make your own footprint.
If you're lucky, you don't need to create your own footprint library. Most boards can be built out of components that fit the standard footprint libraries.
If you create a new library, please please please embed a description of the library -- your name, email address, web page, the date it was created, the date of this revision, etc. Create an extra dummy component named "__about" with a bunch of "top overlay" silkscreen strings that list this text information ("metadata"). If you use the ".ddb" format, put a simple text file "readme.txt" in each ".ddb" database with this information.
When making a new footprint, it helps to
A: I right-click on the name of the component (in the left pane of the footprint editor), and choose "copy". No more clicks needed. Then I switch to my own personal libraries, right-click in that left pane, and choose "paste". Then rename it. In the footprint editor, I think this is the same as using ``Edit | Copy Component'', then flipping to my own library .ddb and doing ``Edit | Paste Component''.
Bug: The footprint I just pasted has the pick point (location 0,0 in the footprint editor) is centered on pin 1, no matter where it was on the original footprint. Manually fix it (see making a new footprint ) .
``First thing you do after "Tools/New Component", is "Tools/Rename Component".'' -- Peter Bennett. ``Using the same name for 2 different footprints is asking for trouble.'' -- David Cary.
footprint design tips: [FIXME: should I move "component footprint design" to its own page, http://massmind.org/techref/app/pwb_design_flow.htm#footprint http://massmind.org/techref/pwb_layers.htm http://massmind.org/techref/app/pwb_libraries.htm ?]
A: Rich Schutz on 2001-08-01 01:50:30 PM wrote:
Mark, We ... Design the lands per IPC then add the extra pad. Do not change the Z-span of the pads. You want the extra pad on the ends to prevent shadowing. ... We add .020" to the outside pad edge for all chip resistors ... add .030" to ... Chip capacitors.
From: rlamoreaux on 2001-05-30 To: "Protel EDA Forum" Subject: Re: [PEDA] SMT Land Pattern Design I have generally used a combined approach which made since with older versions of Protel, and is a little more difficult with newer. Older versions of Protel had two spacings, one for large components and the other for small. I made the small components like 0805 parts so the silkscreen would overlap and form one 10 mil line at the proper spacing, and large components had a spacing from their outmost pad or silkscreen. This worked good for me. This was useful since it is hard to draw an outline for a small part unless it is on the edge of the placement area, and some large parts can look strange with a lot of silkscreen around them. With the current version of Protel I will create a class for small components and a class for large to do the same thing. Then I can create rules to set the proper spacing for all the different types of parts.
Common footprints people design:
Most people put their company logo into their database:
From: HxEngr on 2000-08-31 12:11:48 PM To: Multiple recipients of list proteledausers Subject: Re: [PROTEL EDA USERS]: Place Graphics into PCB In a message dated 8/31/00 12:55:49 PM Eastern Daylight Time, RTupa writes: > Is there a way to place Graphics like a Company Logo into a PCB Data > Base? > One way that I've used is to build a footprint which contains the appropriate shapes, text, or whatever, either in the copper layers or the silkscreen. I even sometimes place a dummy "testpoint" part which calls for that footprint, in an obscure corner of the schematic so it doesn't get removed if I fully update the netlist. Biggest drawbag is that you can't handily scale the logo this way, so you might need to make several of different sizes, depending upon your needs. Steve Hendrix
Abd ul-Rahman Lomax on 2000-10-19 05:26:17 PM said [witty remarks ruthlessly snipped and other edits by the FAQ maintainer]:
At 08:11 AM 8/31/00 +0000, Ron Tupa wrote: >Is there a way to place Graphics like a Company Logo into a PCB Data >Base? Yes. ... There are two utilities. One of them is free, convert.zip, ... converts BMP to Protel ... Connect to www.idrive.com. Visit abdlomax. Activate the link under Storage, Convert.zip. Check the box beside Convert.zip and push the Download button. Unfortunately, I just checked and idrive is not allowing guest access, temporarily, they claim. ... So I'm uploading it also to the filespace for firstname.lastname@example.org. That filespace is publically accessible, you don't have to be a subscriber to email@example.com. (But I do recommend that all Protel users subscribe to the list; it's a backup list for this (techserv) list, which is occasionally down. There are about fifty subscribers to the backup list at this point; please do not post to protel-users except in an emergency, unless the association decides to do something else with protel-users.) Convert.zip contains a utility to convert BMP files to Protel format. http://www.egroups.com/files/protel-users/Convert.zip The other program is: >PCBLOGO costs $15(US) and is available from Henry Velthuizen, ><hfav at paradise.net.nz>, 104 Upper Fitzherbert Road, Wainuiomata, New Zealand. I'll also remind users that there is an ad list for Protel-related products and services: firstname.lastname@example.org. Like all the egroups lists, that list has an archive, so postings to the list will remain accessible for a long time. ... Note that there are not very many subscribers to protel-users-ads, but the egroups archives are indexed by major search engines and the archives are publically accessible. So an ad there may reach an audience far beyond the subscription base. For an example, search on www.google.com (my favorite search engine) for "Protel resale" and you will find pages from the mailing list email@example.com. Following up that search could save a Protel buyer upwards of $3000.... Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433
Brian Guralnick has written:
PicToGBR.zip - 3kb -> source & instructions on how to convert a 256 shade gray image to Gerber.
pictogerberexample.zip - 182kb -> 3 images already converted into Gerber, both in circle mode & square mode. Select 'TopOverlay layer', then import.
If you use BGAs, you might want to use a footprint that includes traces "pre-routed" from the balls to the perimeter of the part. (Unfortunately, there is a bug in the 99SE auto-router -- the auto-router sometimes rips up those pre-routed traces. Work-around: change the footprint to any other arbitrary footprint, then change back to the correct footprint to re-load that footprint from the library. Then
"Design | Netlist Manager | Menu | Update Free Primitives From Component Pads"
to get those pre-routed traces connected to the correct net.
Q1a: How do I make a custom pad shape ? (I need something other than the simple pads shapes built-in to Protel: "circle", "rectangle", "oval", and "octagon")
A1: Build the custom pad shape out of several overlapping pads on the top layer (and optionally a through-hole pad on the multilayer). Assign them all the same reference designator.
A2: For even more flexibility, build the custom pad shape out of overlapping fills on *both* the top paste mask layer *and* the top copper layer. Place a small simple pad touching those fills. (Either a surface-mount pad on the top layer or through-hole pad on the multilayer).
Q1b: I tried that, but when I placed that footprint on my PWB, it lights up bright green with lots of DRC errors.
A1b: run "Design | Netlist Manager | Menu | Update Free Primitives From Component Pads" and run another DRC check.
One under-appreciated ``component'' is the ``virtual short'', also known as a ``star point'' which can be used as a ``star ground''. (However, many people point out that one solid unsplit ground plane is better than a "star ground". )
Q: ``Isn't there some way to put ... a trace on the board that is ignored for DRC checks ? ... Also, I want to put jumpers on my board that are shorted on the PCB. That means that to use the jumper I have to cut the trace on the PCB. How do I do this? It is the same type of question. '' -- Russell
Since you want the 2 nets to connect at one and only one place, symbolize that place on your schematic with a 0 Ohm resistor symbol or ``Create a schematic symbol, call it TIE, that looks like a short bar with a pin at each end. When placing the symbol on the schematic, you will be able to preserve your individual net names.'' -- John Lemburg on 2001-01-31. Then give that component the special "TIE" footprint.
Abd ul-Rahman Lomax on 2000-08-21 01:21:58 PM
a shorting component that is open to DRC and shorted in the actual copper. The basic idea is to use a very small distance between [``surface mount''] pads or fills (pads are better because they can be named). In the schematic is an ordinary jumper, between, for example, GND and GNDA. The pads have a dimension in the contact direction which is, say, .002 mil (yes, 2 microinches) short of contact, and a Design Rule is created to allow those two pads to be so close without generating a clearance error. Once such a component is made, it can be used for any PCB. If one forgets to make the Design Rule, one gets reminded. ...
So one has control *from the schematic* over the shorting of nets; it is a single-point short -- which is what is ordinarily needed -- and additional shorts will be reported as DRC errors (unless, of course, one has placed more than one short), and the position of the short is clearly and easily controlled. It's easy to implement star grounds with this, by having several of these shorting components side-by-side. (These are non-BOM components....) ...
For prototype work, an ordinary jumper [footprint] can be used instead of the shorting component, allowing the replacement of the short by an inductor or resistor; the jumper is then replaced with the shorting footprint when the production gerbers are created.
Geoff Harland adds,
Doing things this way means that the implementation is *also* documented by the schematic file, and it is not necessary to tolerate DRC errors (in the PCB file), or to add any shorting tracks *after* running a DRC check (and before producing Gerber files).
To prevent [the TIE component] from being imaged on the Gerber file for the Paste Mask layer, set the Paste Mask expansion value to a sufficiently negative value so as to mask these pads on this layer. (This can be done with a Design Rule, or from the 'Pad' dialog box invoked after clicking on each of the pads concerned.) And unless you want the copper in the area of these pads to be exposed on the actual PCB, similarly mask these pads on the Solder Mask layer as well. (Again, either by defining a Design Rule, or from the 'Pad' dialog box.)
Other people use this PWB footprint:
``Create a PCB shape for TIE that looks like interleaved fingers of trace, like 4 from one end and 5 from the other, so that the fingers are not electrically connected when the board is fab'ed. The TIE pattern can be made large or small -- or very small -- depending on the ground currents. The TIE PCB shape has two connections -- just like the schematic symbol. ...
Place two TIE patterns, one connecting PS ground to GNDA and the other connecting PS ground to GNDD, very near the common ground point at the DC-DC converter on the board, on the back side or non-component side. ...
When you build first article, mask off the TIE patterns so they stay electrically open. Then when you check for ground integrity and non-pollution of that ground system, you can be absolutely sure that there are no sneak paths! ...
Remove the mask from the TIE patterns and apply solder. Now they are connected. In production, they will always be soldered and thus connected. ... Simply passing the board through wave soldering does the "short" by wetting the TIE fingers. ...
Any time you want to verify grounds are really connected at one point, at PS holy ground, simply solder-suck the TIE pattern or patterns for your test. Solder them back when you are done.''
-- John Lemburg on 2001-01-31.
Leaving the shorting to the very end of the process, with a gap that will survive fabrication, could make test easier. ... if the bare board is tested, the TIE method should detect additional shorts taking place in fabrication between the grounds, shorts that could serious affect noise performance; the virtual short method would not. ... However, for RF components which are never going to see the wave, a virtual short may be superior. ... Zero-ohm resistors or jumpers ... require the addition of a component or some additional operation to implement the short [compared to the virtual short]. If it considered desireable to have the short easily removed and replaced, I'd recommend a simple two-pin .100 spacing jumper; berg pins can be used, or a wire can be inserted and soldered or cut or resoldered.
-- Abd ul-Rahman Lomax on 2001-01-31
See "How can I join two nets together on a Schematic and then on the PCB without creating an ERC and a DRC violation, respectively?" http://www.protel.com/resources/kb/kb_item.asp?ID=2097 ( was http://www.protel.com/kb/kb_item.asp?ID=2097 was http://www.protel.com/kb/rdc2097.htm ) for another work-around.
Both of these methods ("virtual short" component; real 0 Ohm resistor component) are used when you want DRC to make sure 2 nets are shorted together at one and only one place. For example, star grounds, the single-point connection between AGND and DGND. They can also help remind us to put the termination resistors at the correct end of a trace. Or connecting only at the 2 "ends" of a planar transformer.
microwave filter designers seem to really like the "virtual short" component.
``There are a number of advantages to [placing a zero Ohm resistor]. At prototype stage you can experiment with the options, such as a direct short between the two grounds, or a resistor, or an inductor. I commonly see a 10 ohm resistor used for this purpose. Another advantage is simplicity. You already know how to do this one. ... It is *much* better to use a zero ohm resistor or one of the other possibilities I will suggest than to merely short the grounds on the board. This would completely conceal any need to keep the grounds isolated (meeting at only a single point) and DRC will not detect such shorts, which could cause the product to fail, and, even worse, such a failure might be marginal and only occur under some conditions. If you have a single-point shorting component, you will not have to worry about this; you won't need to carefully track down your net's meandering to be sure it is isolated everywhere except the one point you want. ... make a design rule which will allow the pads of a specific component to be within .001 mil of each other. Yes, 1 microinch. Since such a gap (1) won't get plotted since the necessary plot resolution is unattainable with printed circuit board level photoplotters, (2) if it were plotted, it would not be fabricated since no fabricator could do this with pc board materials even if he tried hard, ... Just as with a zero-ohm resistor, this goes on the schematic and has the appropriate footprint assigned to it. ... The same concept can be used for such fauna as RF inductors that are only copper pattern on the board, anything that must be treated as a component for net list purposes, but which actually shorts, contrary to the net list. I have not discovered a down side to this procedure. ... There are also some tricks that can be done with plated-through holes. It is very easy and fast to drill out the plating in a hole to open a connection which depends on that plating. Because the hole guides the drill, one is less likely to slip and damage something else on the board.... ''
-- Abd ul-Rahman Lomax on 2001-01-26 08:13:51 PM
Another description of the same thing:
-1- I defined a schematic symbol named TIE with 2 (unconnected) pins but graphically showing clearly the desired connection. -2- I defined a PCB library foot-print TIE with 2 tracks separated by a ~ 0.00003mm gap -3- I defined a "Component Class" for TIE -4- I defined a "Clearance Constraint" of 0.00003mm for Class TIE I just ask to my PCB manufacturer if a 0.00003mm gap will be under the resolution of his process, and it's 100% the case. I don't have error with schematic (nets are unconnected) and PCB (no net short-circuit or clearance violation)
-- Rudolf Schaffer on 2001-01-30 02:31:43 AM
Brad Velander on 2000-08-21 11:20:15 AM
Just for your reference we use the following pattern. We have two triangular drawn pads separated by a diagonal gap of 10 mils. The triangular pad & diagonal gap makes the visual presentation of the shorting jumper somewhat unique and less likely to be confused with other pads or features. There is no soldermask between the two pads. Finally we use a round circular silkscreen around the pads.
http://geocities.com/siliconvalley/way/5807/dat.html used to point to a couple of CAD libraries ... have they moved elsewhere?
Protel users FAQ
Alas, I doubt this Hirose connector in the standard libraries. Most likely you will have to build the footprint yourself, using the "Recommended PCB mounting pattern" described in the datasheet, adding the "pin 1 indicator" and other things recommended by the Footprint Library design tips.
Since Digikey sells this part, the easiest way to get its datasheet is to look it up on Digikey, find its part page, and click on "Technical information" and "Datasheet".
Does that answer your question?
|file: /Techref/app/PWB_libraries.htm, 38KB, , updated: 2013/8/19 10:42, local time: 2017/5/22 16:13,
|©2017 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://massmind.org/techref/app/PWB_libraries.htm"> libraries of schematic symbols and layout footprints</A>
|Did you find what you needed?|
Welcome to massmind.org!
Welcome to massmind.org!